armv8: fsl-lsch3: Rewrite MMU translation table entriesThis patch rewrites MMU translation table entries. To start, all tableentries are written as "invalid", then "device-ngnrnr" and "normal" are
armv8: fsl-lsch3: Rewrite MMU translation table entriesThis patch rewrites MMU translation table entries. To start, all tableentries are written as "invalid", then "device-ngnrnr" and "normal" arewritten to the entries to enable access to specific addresses.Signed-off-by: Alison Wang <alison.wang@freescale.com>Signed-off-by: York Sun <yorksun@freescale.com>
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armv8: Fix TCR macros for shareability attributeFor ARMv8, outer shareable is 0b10, inner shareable is 0b11 at bitposition [13:12] of TCR_ELx register.Signed-off-by: Zhichun Hua <zhichun.hua@fre
armv8: Fix TCR macros for shareability attributeFor ARMv8, outer shareable is 0b10, inner shareable is 0b11 at bitposition [13:12] of TCR_ELx register.Signed-off-by: Zhichun Hua <zhichun.hua@freescale.com>Signed-off-by: York Sun <yorksun@freescale.com>
armv8/fsl-lsch3: Change normal memory shareabilityAccording to hardware implementation, a single outer shareable globalcoherence group is defined. Inner shareable has not bee enabled.Signed-off-
armv8/fsl-lsch3: Change normal memory shareabilityAccording to hardware implementation, a single outer shareable globalcoherence group is defined. Inner shareable has not bee enabled.Signed-off-by: York Sun <yorksun@freescale.com>
ARMv8: Adjust MMU setupMake MMU function reusable. Platform code can setup its own MMU tables.Signed-off-by: York Sun <yorksun@freescale.com>CC: David Feng <fenghua@phytium.com.cn>
arm64: core supportRelocation code based on a patch by Scott Wood, which is:Signed-off-by: Scott Wood <scottwood@freescale.com>Signed-off-by: David Feng <fenghua@phytium.com.cn>
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