| #
48d2fc47 |
| 30-Oct-2016 |
Tom Rini <trini@konsulko.com> |
Merge branch 'sun9i-a80-spl' of http://git.denx.de/u-boot-sunxi
|
| #
7962a8d5 |
| 28-Oct-2016 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
sunxi: add initial clock setup for sun9i for SPL
This is a cleaned up version set_pll() from Allwinner's boot0 source
(bootloader/basic_loader/bsp/bsp_for_a80/common/common.c).
[wens@csie.org: Adde
sunxi: add initial clock setup for sun9i for SPL
This is a cleaned up version set_pll() from Allwinner's boot0 source
(bootloader/basic_loader/bsp/bsp_for_a80/common/common.c).
[wens@csie.org: Added commit message; style cleanup]
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
show more ...
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| #
297bb9e0 |
| 28-Oct-2016 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
sunxi: DRAM initialisation for sun9i
This adds DRAM initialisation code for sun9i, which calculates the
appropriate timings based on timing information for the supplied
DDR3 bin and the clock speeds
sunxi: DRAM initialisation for sun9i
This adds DRAM initialisation code for sun9i, which calculates the
appropriate timings based on timing information for the supplied
DDR3 bin and the clock speeds used.
With this DRAM setup, we have verified DDR3 clocks of up to 792MHz
(i.e. DDR3-1600) on the A80-Q7 using a dual-channel configuration.
[wens@csie.org: Moved dram_sun9i.c to arch/arm/mach-sunxi/; style cleanup]
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
[hdegoede@redhat.com: Drop some huge non-documenting #if 0 ... #endif blocks]
[hdegoede@redhat.com: Fix checkpatch warnings]
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
show more ...
|
| #
b1f7ecc9 |
| 31-May-2015 |
Tom Rini <trini@konsulko.com> |
Merge branch 'master' of http://git.denx.de/u-boot-sunxi
|
| #
d0f42003 |
| 26-May-2015 |
Roy Spliet <r.spliet@ultimaker.com> |
sunxi: Match sun4i, sun6i, sun9i CCI definitions for NAND and DMA
Make sure definitions for NAND clock and DMA gate bits are the same
across boards.
Signed-off-by: Roy Spliet <r.spliet@ultimaker.co
sunxi: Match sun4i, sun6i, sun9i CCI definitions for NAND and DMA
Make sure definitions for NAND clock and DMA gate bits are the same
across boards.
Signed-off-by: Roy Spliet <r.spliet@ultimaker.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
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|
| #
e72d3443 |
| 13-Feb-2015 |
Stefano Babic <sbabic@denx.de> |
Merge branch 'master' of git://git.denx.de/u-boot
|
| #
3b95288a |
| 23-Jan-2015 |
Tom Rini <trini@ti.com> |
Merge branch 'master' of http://git.denx.de/u-boot-sunxi
|
| #
e35377d7 |
| 14-Jan-2015 |
Hans de Goede <hdegoede@redhat.com> |
sun9i: Add clock_sun9i.h with ccu register layout for sun9i
Add a headerfile with the sun9i ccu register layout.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@helli
sun9i: Add clock_sun9i.h with ccu register layout for sun9i
Add a headerfile with the sun9i ccu register layout.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
show more ...
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