| #
9ec61dbc |
| 01-Sep-2017 |
Tom Rini <trini@konsulko.com> |
Merge branch 'master' of git://git.denx.de/u-boot-sunxi
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| #
de9b1771 |
| 23-Aug-2017 |
Maxime Ripard <maxime.ripard@free-electrons.com> |
mmc: sunxi: Support new mode
Almost all of the newer Allwinner SoCs have a new operating mode for the
eMMC clocks that needs to be enabled in both the clock and the MMC
controller.
Details about th
mmc: sunxi: Support new mode
Almost all of the newer Allwinner SoCs have a new operating mode for the
eMMC clocks that needs to be enabled in both the clock and the MMC
controller.
Details about that mode are sparse, and the name itself (new mode vs old
mode) doesn't give much details, but it seems that the it changes the
sampling of the MMC clock. One side effect is also that it divides the
parent clock rate by 2.
Add support for it through a Kconfig option.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
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| #
40345e9e |
| 01-Apr-2016 |
Tom Rini <trini@konsulko.com> |
Merge branch 'master' of http://git.denx.de/u-boot-sunxi
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| #
93bac953 |
| 29-Mar-2016 |
Chen-Yu Tsai <wens@csie.org> |
sunxi: clk: Fix USB PHY clock macros for A83T
The A83T has 3 PHYs, the last one being HSIC, which has 2 clocks.
Also there is only 1 OHCI.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: H
sunxi: clk: Fix USB PHY clock macros for A83T
The A83T has 3 PHYs, the last one being HSIC, which has 2 clocks.
Also there is only 1 OHCI.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
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| #
a5d4785c |
| 11-Dec-2015 |
Tom Rini <trini@konsulko.com> |
Merge branch 'master' of http://git.denx.de/u-boot-sunxi
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| #
f542948b |
| 28-Nov-2015 |
vishnupatekar <vishnupatekar0510@gmail.com> |
sunxi: clk: add basic clocks for A83T
Add basic clocks pll1, pll5, and some default values from allwinner u-boot.
Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
[hdegoede@redhat.com] F
sunxi: clk: add basic clocks for A83T
Add basic clocks pll1, pll5, and some default values from allwinner u-boot.
Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
[hdegoede@redhat.com] Fix PLL6 init to run at 600 MHz instead of 288 MHz,
fixing the mmc support not working
[hdegoede@redhat.com] Fix PLL init code to properly wait for the PLL-s to
stabilize, fixing cold-booting directly from sdcard not working
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
show more ...
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