| #
b9756a5b |
| 15-Nov-2018 |
Kever Yang <kever.yang@rock-chips.com> |
rockchip: boot0: init gd as null in TINY_TPL
Init gd to NULL in case someone using it. For example, below patch using gd in debug_uart_init: 064eb49314 serial: ns16550: support using pre-loader seri
rockchip: boot0: init gd as null in TINY_TPL
Init gd to NULL in case someone using it. For example, below patch using gd in debug_uart_init: 064eb49314 serial: ns16550: support using pre-loader serial
Change-Id: Iee71dc8bc9168a0364598a3b4027807cba522594 Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
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| #
c7b9ee6b |
| 09-Nov-2018 |
Kever Yang <kever.yang@rock-chips.com> |
rockchip: rk3399: add tpl support in Kconfig
Rockchp platform suppose to use TPL(run in SRAM) as dram init and SPL(run in DDR SDRAM) as pre-loader, so that the SPL would not be limited by SRAM size.
rockchip: rk3399: add tpl support in Kconfig
Rockchp platform suppose to use TPL(run in SRAM) as dram init and SPL(run in DDR SDRAM) as pre-loader, so that the SPL would not be limited by SRAM size.
Change-Id: Ib4115dbf6679fd4649e694d069a6489346112a97 Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
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| #
a3f8c59f |
| 28-Aug-2018 |
Zhihuan He <huan.he@rock-chips.com> |
rockchip: ARM: tpl: add TPL_TINY_FRAMEWORK flow for arm
If sram size is small for TPL build, it can defined CONFIG_TPL_TINY_FRAMEWORK to reduce TPL size. For ARM if defined CONFIG_TPL_TINY_FRAMEWORK
rockchip: ARM: tpl: add TPL_TINY_FRAMEWORK flow for arm
If sram size is small for TPL build, it can defined CONFIG_TPL_TINY_FRAMEWORK to reduce TPL size. For ARM if defined CONFIG_TPL_TINY_FRAMEWORK when build TPL, after save_boot_params(), it jump to board_init_f() directly, then return to maskrom. and stack also use maskrom defined result, never change the SP.
Change-Id: I9a90d031a5d200f86c437175e9ea47e8a34062ac Signed-off-by: Zhihuan He <huan.he@rock-chips.com>
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| #
37e5dcc8 |
| 05-Jul-2018 |
YouMin Chen <cym@rock-chips.com> |
rockchip: ARM64: tpl: modify TPL_TINY_FRAMEWORK flow to reduce code size
If sram size is small for TPL build, it can defined CONFIG_TPL_TINY_FRAMEWORK to reduce TPL size. For ARM64 if defined CONFIG
rockchip: ARM64: tpl: modify TPL_TINY_FRAMEWORK flow to reduce code size
If sram size is small for TPL build, it can defined CONFIG_TPL_TINY_FRAMEWORK to reduce TPL size. For ARM64 if defined CONFIG_TPL_TINY_FRAMEWORK when build TPL, after save_boot_params(), it jump to board_init_f() directly, then return to maskrom. and stack also use maskrom defined result, never change the SP.
Change-Id: I80dc414fcc276f5ea2c09afd6d1eb16e2f2f4cf6 Signed-off-by: YouMin Chen <cym@rock-chips.com>
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| #
9d33a67d |
| 18-Dec-2017 |
Kever Yang <kever.yang@rock-chips.com> |
UPSTREAM: rockchip: update boot0 hook
Rockchip SoCs only need boot0 hook at SPL, and the U-Boot proper do not need it.
The very beginning of U-Boot proper is different between armv7 and armv8: armv
UPSTREAM: rockchip: update boot0 hook
Rockchip SoCs only need boot0 hook at SPL, and the U-Boot proper do not need it.
The very beginning of U-Boot proper is different between armv7 and armv8: armv7 start with ARM_VECTORS while armv8 start with 'b reset'.
Here is the map of very beginning for all cases: armv7 SPL: TAG(overwrite 'b 1f')+'b reset' + ARM_VECTORS armv7 U-Boot: ARM_VECTORS armv8 SPL: TAG(overwrite 'b 1f')+'b reset' + Reserved_iram(rk3399) armv8 U-Boot: 'b reset'
Change-Id: I433ccd2e09f32fa3f1892953d67650a99dac39bc Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com> (cherry picked from commit 270288544e12c7c98e4bc9a5b121517ba0a959d2)
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| #
82c369d0 |
| 05-Jan-2018 |
Kever Yang <kever.yang@rock-chips.com> |
Revert "rockchip: update boot0 hook"
This reverts commit 7a4d1b540601cf674de4f85400b71859f689c9b3.
Change-Id: I6f2f5ac92b83129a816a409f669c4ceb2c36b64b Signed-off-by: Kever Yang <kever.yang@rock-ch
Revert "rockchip: update boot0 hook"
This reverts commit 7a4d1b540601cf674de4f85400b71859f689c9b3.
Change-Id: I6f2f5ac92b83129a816a409f669c4ceb2c36b64b Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
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| #
7a4d1b54 |
| 10-Nov-2017 |
Kever Yang <kever.yang@rock-chips.com> |
rockchip: update boot0 hook
armv7 SPL: TAG(overwrite 'b 1f')+'b reset' + ARM_VECTORS armv7 U-Boot: ARM_VECTORS armv8 SPL: TAG(overwrite 'b 1f')+'b reset' + Reserved_iram(rk3399) armv8 U-Boot: 'b res
rockchip: update boot0 hook
armv7 SPL: TAG(overwrite 'b 1f')+'b reset' + ARM_VECTORS armv7 U-Boot: ARM_VECTORS armv8 SPL: TAG(overwrite 'b 1f')+'b reset' + Reserved_iram(rk3399) armv8 U-Boot: 'b reset'
Change-Id: I0ebb3e57d138c02e8781e50dbe775925cd0d71e0 Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
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| #
dff737c4 |
| 10-Oct-2017 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
UPSTREAM: rockchip: boot0 hook: support early return for RK3188/RK3066-style BROM
Some Rockchip BROM versions (e.g. the RK3188 and RK3066) first read 1KB data from NAND into SRAM and executes it. Th
UPSTREAM: rockchip: boot0 hook: support early return for RK3188/RK3066-style BROM
Some Rockchip BROM versions (e.g. the RK3188 and RK3066) first read 1KB data from NAND into SRAM and executes it. Then, following a return to bootrom, the BROM loads additional code to SRAM (not overwriting the first block read) and reenters at the same address as the first time.
To support booting either a TPL (on the RK3066) or SPL (on the RK3188) using this model of having to count entries, this commit adds code to the boot0 hook to track the number of entries and handle them accordingly.
Change-Id: Ib7c0e9fc517ff7c040ba948ea4a570538d623760 Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Signed-off-by: Paweł Jarosz <paweljarosz3691@gmail.com> Tested-by: Andy Yan <andy.yan@rock-chips.com> Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
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| #
5577f854 |
| 10-Oct-2017 |
Kever Yang <kever.yang@rock-chips.com> |
FROMLIST: rockchip: boot0: align to 0x20 for armv7 '_start'
The '_start' is using as vector table base address, and will write to VBAR register, so it needs to be aligned to 0x20 for armv7.
Signed-
FROMLIST: rockchip: boot0: align to 0x20 for armv7 '_start'
The '_start' is using as vector table base address, and will write to VBAR register, so it needs to be aligned to 0x20 for armv7.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com> [Updated to current code base:] Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Change-Id: If3c151e7071f8d9556827bb05cfd38892b1c17f3 Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
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| #
733d51d5 |
| 10-Oct-2017 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
FROMLIST: arm: boot0 hook: move boot0 hook before '_start'
The boot0 hook on ARM does not insert its payload before the vector table. This is both a mismatch with thec comment above it and contradic
FROMLIST: arm: boot0 hook: move boot0 hook before '_start'
The boot0 hook on ARM does not insert its payload before the vector table. This is both a mismatch with thec comment above it and contradict usage of the boot0 hook on ARM64.
To fix this (and unify the semantics for ARM and ARM64), we change the boot0-hook semantics on ARM to match those on ARM64: (1) if a boot0-hook is present it is inserted at the start of the image (2) if a boot0-hook is present, emitting the ARM vector table (and the _start) symbol are suppressed in vectors.S and the boot0-hook has full control over where and when it wants to emit these
Change-Id: Ibd3b7c18a6a32f90372d315659f68511d92ca648 Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
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| #
700f3108 |
| 11-Jul-2017 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
rockchip: spl: make boot0 hook TPL safe
When building for a TPL/SPL setup (e.g. on the RK3368), we need the TPL stage to have the extra space for for the 'Rockchip SPL name' (i.e. 'RK33' word). Yet
rockchip: spl: make boot0 hook TPL safe
When building for a TPL/SPL setup (e.g. on the RK3368), we need the TPL stage to have the extra space for for the 'Rockchip SPL name' (i.e. 'RK33' word). Yet, the SPL will start execution at its first word (i.e. the first word in the SPL binary needs to be a valid instruction). To make things a bit more involved, CONFIG_SPL_BUILD is defined both for the SPL and the TPL stage.
To avoid having to explicitly test for the first stage (TPL, if and only if TPL and SPL are built, SPL otherwise), this commit modifies the sequence to repeat the 'b reset' (instead of reserving 4 bytes of undefined space) at the start of the boot0 hook: if overwritten (and execution starts at the second word), the first instruction is still a 'b reset'... if not overwritten, we start on a 'b reset' as well.
This solution wouldn't even require the check whether we are in the SPL/TPL build (i.e. CONFIG_SPL_BUILD), but we leave this check in for documentation purposes.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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| #
1f5541c8 |
| 10-May-2017 |
Tom Rini <trini@konsulko.com> |
Merge git://git.denx.de/u-boot-rockchip
This adds a new firefly-rk3399 board, MIPI support for rk3399 and rk3288, rk818 pmic support, mkimage improvements for rockchip and a few other things.
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| #
fa1392a2 |
| 20-Apr-2017 |
Kever Yang <kever.yang@rock-chips.com> |
rockchip: reserve memory for rk3399 ATF data
There are 3 regions used by rk3399 ATF: - bl31 code, located at 0x10000; - cortex-m0 code and data, located at 0xff8c0000; - bl31 data, located at 0xff8c
rockchip: reserve memory for rk3399 ATF data
There are 3 regions used by rk3399 ATF: - bl31 code, located at 0x10000; - cortex-m0 code and data, located at 0xff8c0000; - bl31 data, located at 0xff8c1000 ~ 0xff8c4000;
SPL_TEXT_BASE starts from 0xff8c2000, we need to reserve memory for ATF data, or else there will be memory corrupt after SPL loads the ATF image.
More detail about cortex-M0 code in ATF: https://github.com/ARM-software/arm-trusted-firmware/commit/ 8382e17c4c6bffd15119dfce1ee4372e3c1a7890
Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
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| #
3d54eabc |
| 15-Mar-2017 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
rockchip: spl: RK3399: use boot0 hook to create space for SPL magic
The SPL binary needs to be prefixed with the boot magic ('RK33' for the RK3399) on the Rockchip platform and starts execution of t
rockchip: spl: RK3399: use boot0 hook to create space for SPL magic
The SPL binary needs to be prefixed with the boot magic ('RK33' for the RK3399) on the Rockchip platform and starts execution of the instruction word following immediately after this boot magic.
This poses a challenge for AArch64 (ARMv8) binaries, as the .text section would need to start on the odd address, violating natural alignment (and potentially triggering a fault for any code that tries to access 64bit values embedded in the .text section).
A quick and easy fix is to have the .text section include the 'RK33' magic and pad it with a boot0 hook to insert 4 bytes of padding at the start of the section (with the intention of having mkimage overwrite this padding with the appropriate boot magic). This avoids having to modify the linker scripts or more complex logic in mkimage.
X-AffectedPlatforms: RK3399-Q7 Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com>
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