History log of /rk3399_rockchip-uboot/arch/arm/include/asm/arch-ls102xa/fsl_serdes.h (Results 1 – 5 of 5)
Revision Date Author Comments
# cbe7706a 26-Sep-2016 Tom Rini <trini@konsulko.com>

Merge git://git.denx.de/u-boot-fsl-qoriq

trini: Drop local memset() from
examples/standalone/mem_to_mem_idma2intr.c

Signed-off-by: Tom Rini <trini@konsulko.com>


# 71fe2225 02-Aug-2016 Hou Zhiqiang <Zhiqiang.Hou@nxp.com>

fsl: serdes: ensure accessing the initialized maps of serdes protocol

Up to now, the function is_serdes_configed() doesn't check if the map
of serdes protocol is initialized before accessing it. The

fsl: serdes: ensure accessing the initialized maps of serdes protocol

Up to now, the function is_serdes_configed() doesn't check if the map
of serdes protocol is initialized before accessing it. The function
is_serdes_configed() will get wrong result when it was called before
the serdes protocol maps initialized. As the first element of the map
isn't used for any device, so use it as the flag to indicate if the
map has been initialized.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

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# 42817eb8 22-Sep-2014 Stefano Babic <sbabic@denx.de>

Merge branch 'master' of git://git.denx.de/u-boot-arm


# 8c9c74e4 10-Sep-2014 Tom Rini <trini@ti.com>

Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq


# d60a2099 05-Sep-2014 Wang Huan <b18965@freescale.com>

arm: ls102xa: Add Freescale LS102xA SoC support

The QorIQ LS1 family is built on Layerscape architecture,
the industry's first software-aware, core-agnostic networking
architecture to offer unpreced

arm: ls102xa: Add Freescale LS102xA SoC support

The QorIQ LS1 family is built on Layerscape architecture,
the industry's first software-aware, core-agnostic networking
architecture to offer unprecedented efficiency and scale.

Freescale LS102xA is a set of SoCs combines two ARM
Cortex-A7 cores that have been optimized for high
reliability and pack the highest level of integration
available for sub-3 W embedded communications processors
with Layerscape architecture and with a comprehensive
enablement model focused on ease of programmability.

Signed-off-by: Alison Wang <alison.wang@freescale.com>
Signed-off-by: Jason Jin <jason.jin@freescale.com>
Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>

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