History log of /rk3399_rockchip-uboot/arch/arm/include/asm/arch-ls102xa/clock.h (Results 1 – 5 of 5)
Revision Date Author Comments
# 457e51cf 17-May-2017 Simon Glass <sjg@chromium.org>

common: arm: freescale: layerscape: Move header files out of common.h

We should not have an arch-specific header file in common.h. Adjust the
board files a little so it is not needed, and drop it.

common: arm: freescale: layerscape: Move header files out of common.h

We should not have an arch-specific header file in common.h. Adjust the
board files a little so it is not needed, and drop it.

Signed-off-by: Simon Glass <sjg@chromium.org>

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# 6e2941d7 17-May-2017 Simon Glass <sjg@chromium.org>

common: freescale: Move arch-specific declarations

The declarations should not be in common.h. Move them to the arch-specific
headers.

Signed-off-by: Simon Glass <sjg@chromium.org>
[trini: Fixup th

common: freescale: Move arch-specific declarations

The declarations should not be in common.h. Move them to the arch-specific
headers.

Signed-off-by: Simon Glass <sjg@chromium.org>
[trini: Fixup thinko defined(FSL_LSCH3) -> defined(CONFIG_FSL_LSCH3)]
Signed-off-by: Tom Rini <trini@konsulko.com>

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# 42817eb8 22-Sep-2014 Stefano Babic <sbabic@denx.de>

Merge branch 'master' of git://git.denx.de/u-boot-arm


# 8c9c74e4 10-Sep-2014 Tom Rini <trini@ti.com>

Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq


# d60a2099 05-Sep-2014 Wang Huan <b18965@freescale.com>

arm: ls102xa: Add Freescale LS102xA SoC support

The QorIQ LS1 family is built on Layerscape architecture,
the industry's first software-aware, core-agnostic networking
architecture to offer unpreced

arm: ls102xa: Add Freescale LS102xA SoC support

The QorIQ LS1 family is built on Layerscape architecture,
the industry's first software-aware, core-agnostic networking
architecture to offer unprecedented efficiency and scale.

Freescale LS102xA is a set of SoCs combines two ARM
Cortex-A7 cores that have been optimized for high
reliability and pack the highest level of integration
available for sub-3 W embedded communications processors
with Layerscape architecture and with a comprehensive
enablement model focused on ease of programmability.

Signed-off-by: Alison Wang <alison.wang@freescale.com>
Signed-off-by: Jason Jin <jason.jin@freescale.com>
Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>

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