ARMv7: Factor out reusable timer_wait from sunxi/psci_sun7i.Stimer_wait is moved from sunxi/psci_sun7i.S, and it can be convertedcompletely into a reusable armv7 generic timer. LS1021A will use it
ARMv7: Factor out reusable timer_wait from sunxi/psci_sun7i.Stimer_wait is moved from sunxi/psci_sun7i.S, and it can be convertedcompletely into a reusable armv7 generic timer. LS1021A will use itas well.Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com>Reviewed-by: Hans de Goede <hdegoede@redhat.com>Reviewed-by: York Sun <yorksun@freescale.com>
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Merge branch 'u-boot/master' into u-boot-arm/master
ARM: highbank: set timer prescaler to 256The 150MHz clock rate gives u-boot time functions problems and there's nobenefit to a fast clock, so lower the rate.Signed-off-by: Rob Herring <rob.herri
ARM: highbank: set timer prescaler to 256The 150MHz clock rate gives u-boot time functions problems and there's nobenefit to a fast clock, so lower the rate.Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Add GPL-2.0+ SPDX-License-Identifier to source filesSigned-off-by: Wolfgang Denk <wd@denx.de>[trini: Fixup common/cmd_io.c]Signed-off-by: Tom Rini <trini@ti.com>
ARMv7: Add register definition of global timerARMv7 has global timer. This provides the register definition of this timer.Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>Signe
ARMv7: Add register definition of global timerARMv7 has global timer. This provides the register definition of this timer.Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
ARMV7: Versatile Express Coretile CortexA9x4 supportAdds support for the ARM quad-core Cortex-A9 processorThis system includes a motherboard(Versatile Express), daughterboard(Coretile), and SOC(
ARMV7: Versatile Express Coretile CortexA9x4 supportAdds support for the ARM quad-core Cortex-A9 processorThis system includes a motherboard(Versatile Express), daughterboard(Coretile), and SOC(Cortex-A9 quad core). The serial port, ethernet,and flash systems work with these additions. The naming conventionis: SOC -> CortexA9 quad core = ca9x4 daughterboard -> Coretile = ct motherboard -> Versatile Express = vxpThis gives ca9x4_ct_vxp.c as the board support file.Signed-off-by: Matt Waddel <matt.waddel@linaro.org>