| fa47a286 | 11-Jan-2012 |
Helmut Raiger <helmut.raiger@hale.at> |
mmc: access mxcmmc from mx31 boards
This patch modifies mxcmmc.c to be used
not only by i.MX27 but also by i.MX31 boards.
Both use the same SD controller, but have different
clock set-ups.
The i.MX2
mmc: access mxcmmc from mx31 boards
This patch modifies mxcmmc.c to be used
not only by i.MX27 but also by i.MX31 boards.
Both use the same SD controller, but have different
clock set-ups.
The i.MX27 imx_get_XXXclock functions are made static to
generic.c and a public mxc_get_clock() function
is provided. Pins, base address and prototypes for
an i.MX31 specific board_init_mmc() are provided.
Some of the i.MX27 clock getters are unused and marked
as such to avoid warnings (./MAKEALL -s mx27), but
the code was left in for future use.
Signed-off-by: Helmut Raiger <helmut.raiger@hale.at>
Acked-by: Stefano Babic <sbabic@denx.de>
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| 3f84108b | 14-Jan-2012 |
Heiko Schocher <hs@denx.de> |
arm, davinci: add workaround for not resetting DMA bus and VPSS modules
The Buffer Logic of VPSS is Not Reset by System Reset Pin, see
http://www.ti.com/lit/er/sprz316b/sprz316b.pdf chapter Advisory
arm, davinci: add workaround for not resetting DMA bus and VPSS modules
The Buffer Logic of VPSS is Not Reset by System Reset Pin, see
http://www.ti.com/lit/er/sprz316b/sprz316b.pdf chapter Advisory 1.2.1
on page 9. Add workaroundcode proposed in the errata.
Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Sandeep Paulraj <s-paulraj@ti.com>
Cc: Tom Rini <tom.rini@gmail.com>
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| f5902179 | 31-Jan-2012 |
Dechesne, Nicolas <n-dechesne@ti.com> |
OMAP SPL: Fix missing timer_init() call in OMAP4 s_init()
In 8775471bb, the call to timer_init() was removed from common code
and put in OMAP3 s_init() function. As a result the boot was broken
on O
OMAP SPL: Fix missing timer_init() call in OMAP4 s_init()
In 8775471bb, the call to timer_init() was removed from common code
and put in OMAP3 s_init() function. As a result the boot was broken
on OMAP4. This patch adds timer_init() in OMAP4 s_init(), that fix
boot on all OMAP4 boards.
Signed-off-by: Nicolas Dechesne <n-dechesne@ti.com>
Tested-by: Robert P. J. Day <rpjday@crashcourse.ca>
Cc: Sandeep Paulraj <s-paulraj@ti.com>
Cc: Tom Rini <trini@ti.com>
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| 0ae05651 | 18-Jan-2012 |
Tom Rini <trini@ti.com> |
OMAP3: Correct get_sdr_cs_offset mask
The function get_sdr_cs_offset reads the CS_CFG register in the SDRC
to determine where CS1 is mapped to. make_cs1_contiguous() will set
CS1 to follow after CS
OMAP3: Correct get_sdr_cs_offset mask
The function get_sdr_cs_offset reads the CS_CFG register in the SDRC
to determine where CS1 is mapped to. make_cs1_contiguous() will set
CS1 to follow after CS0. The CS_CFG register has values in bits 9:8
and 3:0 but we had erroneously been testing 5:4 and 3:0 resulting in
incorrect offsets on platforms with less than 128MB as 3:0 describe
128MB hunks and 9:8 describe 32MB offsets after the 128MB hunk.
Tested-by: Grant Erickson <marathon96@gmail.com>
Signed-off-by: Tom Rini <trini@ti.com>
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| 20470511 | 24-Jan-2012 |
Pali Rohár <pali.rohar@gmail.com> |
arm: omap3: Define save_boot_params in lowlevel_init.S for SPL only
Wrap the function save_boot_params with CONFIG_SPL_BUILD. This will
allow non-SPL boards to define their own save_boot_params fun
arm: omap3: Define save_boot_params in lowlevel_init.S for SPL only
Wrap the function save_boot_params with CONFIG_SPL_BUILD. This will
allow non-SPL boards to define their own save_boot_params functions
in U-Boot itself.
Signed-off-by: Pali Rohár <pali.rohar@gmail.com>
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| d652a344 | 16-Jan-2012 |
Ben Gardiner <bengardiner@nanometrics.ca> |
arm, davinci: add PLL0 prediv to da850 lowlevel setup
The OMAP-L138 has a pre-divider available on PLL0.
Add support to da850_lowlevel.c for configuring PLL0's pre-divider. This is
to achieve certa
arm, davinci: add PLL0 prediv to da850 lowlevel setup
The OMAP-L138 has a pre-divider available on PLL0.
Add support to da850_lowlevel.c for configuring PLL0's pre-divider. This is
to achieve certain OPP's -- e.g. the 372MHz OPP used also by Linux.
Signed-off-by: Ben Gardiner <bengardiner@nanometrics.ca>
Cc: Christian Riesch <christian.riesch@omicron.at>
CC: Heiko Schocher <hs@denx.de>
Cc: Sandeep Paulraj <s-paulraj@ti.com>
Cc: Tom Rini <tom.rini@gmail.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Acked-by: Heiko Schocher <hs@denx.de>
Acked-by: Christian Riesch <christian.riesch@omicron.at>
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| bd29cb05 | 09-Jan-2012 |
Simon Glass <sjg@chromium.org> |
tegra2: Enable data cache
This enables the data cache on Tegra2 boards.
As discussed on the list, this is better off in the Tegra2 cpu code than in a
particular vendor directory. We should be safe
tegra2: Enable data cache
This enables the data cache on Tegra2 boards.
As discussed on the list, this is better off in the Tegra2 cpu code than in a
particular vendor directory. We should be safe turning on the cache for all
Tegra2 boards.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
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| cf06b139 | 11-Jan-2012 |
Simon Glass <sjg@chromium.org> |
tegra: Add SDMMC support to funcmux
This adds support for SDMMC ports to the funcmux. Only one
option is supported: FUNCMUXO_SDMMC_8BIT which selects an 8-bit
wide SDIO interface where available.
S
tegra: Add SDMMC support to funcmux
This adds support for SDMMC ports to the funcmux. Only one
option is supported: FUNCMUXO_SDMMC_8BIT which selects an 8-bit
wide SDIO interface where available.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
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| 8a1133c6 | 11-Jan-2012 |
Simon Glass <sjg@chromium.org> |
tegra: Add I2C support to funcmux
Add support to funcmux for selecting I2C functions and programming
the pinmux appropriately.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warre
tegra: Add I2C support to funcmux
Add support to funcmux for selecting I2C functions and programming
the pinmux appropriately.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
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| 2faf1863 | 11-Jan-2012 |
Simon Glass <sjg@chromium.org> |
tegra: Add enum to select from available funcmux configs
We want to give a name to each available funcmux config. For now we just
use the pin group names (even through it is verbose) since there see
tegra: Add enum to select from available funcmux configs
We want to give a name to each available funcmux config. For now we just
use the pin group names (even through it is verbose) since there seems
to be nothing better.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
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| d693969d | 11-Jan-2012 |
Simon Glass <sjg@chromium.org> |
tegra: Adjust funcmux config test to permit expansion
We want to support config options other than zero, so move the test to the
end to allow intermediate code to OK such a config.
Signed-off-by: S
tegra: Adjust funcmux config test to permit expansion
We want to support config options other than zero, so move the test to the
end to allow intermediate code to OK such a config.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
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| 9057e652 | 06-Jan-2012 |
Stephen Warren <swarren@nvidia.com> |
tegra2: Fix default RAM size selection in odmdata
A value of 0 in the odmdata RAM size field means default, which is 512MB
not 1GB. Fix this. For reference, see:
http://nv-tegra.nvidia.com/gitweb/?
tegra2: Fix default RAM size selection in odmdata
A value of 0 in the odmdata RAM size field means default, which is 512MB
not 1GB. Fix this. For reference, see:
http://nv-tegra.nvidia.com/gitweb/?p=linux-2.6.git;a=blob;\
f=arch/arm/mach-tegra/odm_kit/query/harmony/tegra_devkit_custopt.h;\
h=1ec7010911454f19a5018952fd245785a62c59ad;\
hb=0e52d7fe25b11a656c376a37890be219470661fb
v2: New patch
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
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| 4850ab9a | 06-Jan-2012 |
Stephen Warren <swarren@nvidia.com> |
tegra2: Fix conflicting pinmux for UARTA
Tegra appears to boot with function UARTA pre-selected on mux
group SDB. If two mux groups are both set to the same function,
it's unclear which group's pins
tegra2: Fix conflicting pinmux for UARTA
Tegra appears to boot with function UARTA pre-selected on mux
group SDB. If two mux groups are both set to the same function,
it's unclear which group's pins drive the RX signals into the
HW module. For UARTA, SDB certainly overrides group IRTX in
practice. To solve this, configure some alternative function on
SDB to avoid the conflict. Also, tri-state the group to avoid
driving any signal onto it until we know what's connected.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
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| b4116ede | 22-Jan-2012 |
Patil, Rachna <rachna@ti.com> |
ARM: AM33XX: Add i2c support
Add i2c driver board hookup for AM335X EVM
Signed-off-by: Chandan Nath <chandan.nath@ti.com>
Signed-off-by: Patil, Rachna <rachna@ti.com> |
| 761ca31e | 04-Jan-2012 |
Andreas Müller <schnitzeltony@gmx.de> |
omap_rev_string: output to stdout
* avoid potential buffer overflows
* allow SPL-build not to output "Texas Instruments Revision detection unimplemented"
Signed-off-by: Andreas Müller <schnitzelton
omap_rev_string: output to stdout
* avoid potential buffer overflows
* allow SPL-build not to output "Texas Instruments Revision detection unimplemented"
Signed-off-by: Andreas Müller <schnitzeltony@gmx.de>
Signed-off-by: Tom Rini <trini@ti.com>
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| 8775471b | 04-Jan-2012 |
Andreas Müller <schnitzeltony@gmx.de> |
OMAP SPL: call timer_init in s_init to make udelay work earlier
Signed-off-by: Andreas Müller <schnitzeltony@gmx.de> |
| 8a8f084e | 09-Jan-2012 |
Chandan Nath <chandan.nath@ti.com> |
ARM:AM33XX: Add SPL support for AM335X EVM
This patch is added to support SPL feature on AM335X
platform. In this patch, MMC1 is configured as boot
device for SPL and support for other devices will
ARM:AM33XX: Add SPL support for AM335X EVM
This patch is added to support SPL feature on AM335X
platform. In this patch, MMC1 is configured as boot
device for SPL and support for other devices will be
added in the next patch series.
Signed-off-by: Chandan Nath <chandan.nath@ti.com>
Signed-off-by: Tom Rini <trini@ti.com>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
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| 876bdd6d | 09-Jan-2012 |
Chandan Nath <chandan.nath@ti.com> |
ARM:AM33XX: Add mmc/sd support
This patch add supports for mmc/sd driver on AM335X platform.
PLL and pinmux configurations for mmc/sd are configured in this
patch.
Signed-off-by: Chandan Nath <chan
ARM:AM33XX: Add mmc/sd support
This patch add supports for mmc/sd driver on AM335X platform.
PLL and pinmux configurations for mmc/sd are configured in this
patch.
Signed-off-by: Chandan Nath <chandan.nath@ti.com>
Signed-off-by: Tom Rini <trini@ti.com>
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| fb072a3e | 09-Jan-2012 |
Chandan Nath <chandan.nath@ti.com> |
ARM:AM33XX: Fix ddr and timer register offset
This patch is added to update incorrect ddr and timer
register offset.
Signed-off-by: Chandan Nath <chandan.nath@ti.com>
Signed-off-by: Tom Rini <trini
ARM:AM33XX: Fix ddr and timer register offset
This patch is added to update incorrect ddr and timer
register offset.
Signed-off-by: Chandan Nath <chandan.nath@ti.com>
Signed-off-by: Tom Rini <trini@ti.com>
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| 715462dd | 05-Jan-2012 |
Nikita Kiryanov <nikita@compulab.co.il> |
omap3: make get_board_rev() function weak
Current get_board_rev() function returns a hard coded value which is
obviously incorrect for the majority of boards.
Allow boards to provide a correct imple
omap3: make get_board_rev() function weak
Current get_board_rev() function returns a hard coded value which is
obviously incorrect for the majority of boards.
Allow boards to provide a correct implementation by making this function
weak.
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
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| fe7104b3 | 29-Dec-2011 |
Aneesh V <aneesh@ti.com> |
omap4: fix boot issue on ES2.0 Panda
Fix boot issue on ES2.0 Panda by tuning some
IO settings. The CONTROL_EFUSE_2 register has
to be over-ridden in software for 4430 boards.
Commit 23e9f0723e48615
omap4: fix boot issue on ES2.0 Panda
Fix boot issue on ES2.0 Panda by tuning some
IO settings. The CONTROL_EFUSE_2 register has
to be over-ridden in software for 4430 boards.
Commit 23e9f0723e48615332119de4f4ec7a833a282628
wrongly did this for CONTROL_EFUSE_1. Reverting
this and doing it for CONTROL_EFUSE_2.
Signed-off-by: Aneesh V <aneesh@ti.com>
Tested-by: Raúl Porcel <armin76@gentoo.org>
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| f2f77458 | 10-Jan-2012 |
Jason Liu <jason.hui@linaro.org> |
imx: mx6q: add aipstz init for off platform periph
Init peripheral access control register of AIPSTZ OPACRx:
Buffer Writes(BW): 0 -> not bufferable,
Supervisor Protect(SP): 0 -> not require su
imx: mx6q: add aipstz init for off platform periph
Init peripheral access control register of AIPSTZ OPACRx:
Buffer Writes(BW): 0 -> not bufferable,
Supervisor Protect(SP): 0 -> not require supervisor privilege level for accesses.
Write Protect(WP): 0 -> allows write accesses.
Trusted Protect(TP): 0 -> allows unstrusted master
Signed-off-by: Jason Liu <jason.hui@linaro.org>
Cc: Stefano Babic <sbabic@denx.de>
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| 8db9eff6 | 09-Jan-2012 |
Zach Sadecki <zach@itwatchdogs.com> |
mx28: fix clearing of IRQs in power init
There are 2 locations in the power init code for the mx28 where IRQs are not being cleared because incorrect methods to clear those bits were being used. Th
mx28: fix clearing of IRQs in power init
There are 2 locations in the power init code for the mx28 where IRQs are not being cleared because incorrect methods to clear those bits were being used. This was causing my board to get stuck waiting for POWER_CTRL_VDD5V_DROOP_IRQ to clear. Using the correct method to clear the IRQs fixes it.
Signed-off-by: Zach Sadecki <zach@itwatchdogs.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Acked-by: Marek Vasut <marek.vasut@gmail.com>
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| bd2e27c0 | 19-Dec-2011 |
Jason Liu <jason.hui@linaro.org> |
i.mx6:imx6q: allign MAC address with burned-in ordering
For the i.mx6q, the burned-in MAC address will be the following odering,
fuse: 0x620[7:0] MAC_ADDR[7:0] ---> mac[5]
fuse: 0x620[15:8]
i.mx6:imx6q: allign MAC address with burned-in ordering
For the i.mx6q, the burned-in MAC address will be the following odering,
fuse: 0x620[7:0] MAC_ADDR[7:0] ---> mac[5]
fuse: 0x620[15:8] MAC_ADDR[15:8] ---> mac[4]
fuse: 0x620[23:16] MAC_ADDR[23:16] ---> mac[3]
fuse: 0x620[31:24] MAC_ADDR[31:24] ---> mac[2]
fuse: 0x630[7:0] MAC_ADDR[39:32] ---> mac[1]
fuse: 0x630[15:8] MAC_ADDR[47:40] ---> mac[0]
This patch also fix the error caculation for the fuse bank[0] address
Signed-off-by: Jason Liu <jason.hui@linaro.org>
Cc: Stefano Babic <sbabic@denx.de>
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| 5bcc6a89 | 20-Dec-2011 |
Fabio Estevam <festevam@gmail.com> |
mx28: Let dram_init be common for mx28
Let dram_init function be a common function, so that other mx28 boards
can reuse it.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Mare
mx28: Let dram_init be common for mx28
Let dram_init function be a common function, so that other mx28 boards
can reuse it.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Marek Vasut <marek.vasut@gmail.com>
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