OMAP5: ddr: Change the ddr device name.

The ddr part name used in OMAP5 ES1.0 soc is a SAMSUNG part and
not a ELPIDA part. So change this.

Signed-off-by: R Sricharan <r.sricharan@ti.com>

OMAP4/5: device: Add support to get the device type.

Add support to identify the device as GP/EMU/HS.

Signed-off-by: R Sricharan <r.sricharan@ti.com>

OMAP4/5: Make the sysctrl structure common

Make the sysctrl structure common, so that it can
be used in generic functions across socs.
Also change the base address of the system control module, to
i

OMAP4/5: Make the sysctrl structure common

Make the sysctrl structure common, so that it can
be used in generic functions across socs.
Also change the base address of the system control module, to
include all the registers and not simply the io regs.

Signed-off-by: R Sricharan <r.sricharan@ti.com>

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OMAP4/5: Make the silicon revision variable common.

The different silicon revision variable names was defined for OMAP4 and
OMAP5 socs. Making the variable common so that some code can be
made gener

OMAP4/5: Make the silicon revision variable common.

The different silicon revision variable names was defined for OMAP4 and
OMAP5 socs. Making the variable common so that some code can be
made generic.

Signed-off-by: R Sricharan <r.sricharan@ti.com>

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OMAP5: hwinit: Add the missing break statement

The break statement is missing in init_omap_revision function, resulting
in a wrong revision identification. So fixing this.

Signed-off-by: R Srichara

OMAP5: hwinit: Add the missing break statement

The break statement is missing in init_omap_revision function, resulting
in a wrong revision identification. So fixing this.

Signed-off-by: R Sricharan <r.sricharan@ti.com>

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OMAP5: palmas: Configure nominal opp vdd values

The nominal opp vdd values as recommended for
ES1.0 silicon is set for mpu, core, mm domains using palmas.

Also used the right sequence to enable the

OMAP5: palmas: Configure nominal opp vdd values

The nominal opp vdd values as recommended for
ES1.0 silicon is set for mpu, core, mm domains using palmas.

Also used the right sequence to enable the vcores as per
a previous patch from Nishant Menon, which can be dropped now.
http://lists.denx.de/pipermail/u-boot/2012-March/119151.html

Signed-off-by: R Sricharan <r.sricharan@ti.com>

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OMAP5: emif/ddr: Change emif settings as required for ES1.0 silicon.

The OMAP5 silicon has new DDR PHY design, which includes a external PHY
as well. So configuring the ext PHY parameters here. Also

OMAP5: emif/ddr: Change emif settings as required for ES1.0 silicon.

The OMAP5 silicon has new DDR PHY design, which includes a external PHY
as well. So configuring the ext PHY parameters here. Also the EMIF timimg
registers and a couple of DDR mode registers needs to be updated based on
the testing from the actual silicon.

Signed-off-by: R Sricharan <r.sricharan@ti.com>

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OMAP5: io: Configure the io settings for omap5430 sevm board.

The control module provides options to set various signal
integrity parameters like the output impedance, slew rate,
load capacitance fo

OMAP5: io: Configure the io settings for omap5430 sevm board.

The control module provides options to set various signal
integrity parameters like the output impedance, slew rate,
load capacitance for different pad groups. Configure these
as required for the omap5430 sevm board.

Signed-off-by: R Sricharan <r.sricharan@ti.com>

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OMAP5: clocks: Change clock settings as required for ES1.0 silicon.

Aligning all the clock related settings like the dpll frequencies, their
respective clock outputs, etc to the ideal values recomme

OMAP5: clocks: Change clock settings as required for ES1.0 silicon.

Aligning all the clock related settings like the dpll frequencies, their
respective clock outputs, etc to the ideal values recommended for
OMAP5430 ES1.0 silicon.

Signed-off-by: R Sricharan <r.sricharan@ti.com>

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OMAP4: scale voltage of core before MPU scales

OMAP4 requires that parent domains scale ahead of dependent domains.
This is due to the restrictions in timing closure. To ensure
a consistent behavior

OMAP4: scale voltage of core before MPU scales

OMAP4 requires that parent domains scale ahead of dependent domains.
This is due to the restrictions in timing closure. To ensure
a consistent behavior across all OMAP4 SoC, ensure that
vdd_core scale first, then vdd_mpu and finally vdd_iva.

As part of doing this refactor the logic to allow for future
addition of OMAP4470 without much ado. OMAP4470 uses different
SMPS addresses and cannot be introduced in the current code
without major rewrite.

Reported-by: Isabelle Gros <i-gros@ti.com>
Reported-by: Jerome Angeloni <j-angeloni@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>

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OMAP4460: TPS Ensure SET1 is selected after voltage configuration

TPS SET0/SET1 register is selected by a GPIO pin on OMAP4460 platforms.
Currently we control this pin with a mux configuration as pa

OMAP4460: TPS Ensure SET1 is selected after voltage configuration

TPS SET0/SET1 register is selected by a GPIO pin on OMAP4460 platforms.
Currently we control this pin with a mux configuration as part of
boot sequence.
Current configuration results in the following voltage waveform:
|---------------| (SET1 default 1.4V)
| --------(programmed voltage)
| <- (This switch happens on mux7,pullup)
vdd_mpu(TPS) -----/ (OPP boot voltage)
--------- (programmed voltage)
vdd_core(TWL6030) -----------------------/ (OPP boot voltage)
Problem 1) |<----- Tx ------>|
timing violation for a duration Tx close to few milliseconds.
Problem 2) voltage of MPU goes beyond spec for even the highest of MPU OPP.

By using GPIO as recommended as standard procedure by TI, the sequence
changes to:
-------- (programmed voltage)
vdd_mpu(TPS) ------------/ (Opp boot voltage)
--------- (programmed voltage)
vdd_core(TWL6030) -------------/ (OPP boot voltage)

NOTE: This does not attempt to address OMAP5 - Aneesh please confirm

Reported-by: Isabelle Gros <i-gros@ti.com>
Reported-by: Jerome Angeloni <j-angeloni@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>

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OMAP3+: Introduce generic logic for OMAP voltage controller

OMAP Voltage controller is used to generically talk to
PMICs on OMAP3,4,5 over I2C_SR. Instead of replicating code
in multiple SoC code, i

OMAP3+: Introduce generic logic for OMAP voltage controller

OMAP Voltage controller is used to generically talk to
PMICs on OMAP3,4,5 over I2C_SR. Instead of replicating code
in multiple SoC code, introduce a common voltage controller
logic which can be re-used from elsewhere.

With this change, we replace setup_sri2c with omap_vc_init which
has the same functionality, and replace the voltage scale
replication in do_scale_vcore and do_scale_tps62361 with
omap_vc_bypass_send_value. omap_vc_bypass_send_value can also
now be used with any configuration of PMIC.

NOTE: Voltage controller controlling I2C_SR is a write-only data
path, so no register read operation can be implemented.

Reported-by: Isabelle Gros <i-gros@ti.com>
Reported-by: Jerome Angeloni <j-angeloni@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>

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ARM:OMAP+:MMC: Add parameters to MMC init

Add parameters to the OMAP MMC initialization function so the board can
mask host capabilities and set the maximum clock frequency. While the
OMAP supports

ARM:OMAP+:MMC: Add parameters to MMC init

Add parameters to the OMAP MMC initialization function so the board can
mask host capabilities and set the maximum clock frequency. While the
OMAP supports a certain set of MMC host capabilities, individual boards
may be more restricted and the OMAP may need to be configured to match
the board. The PRG_SDMMC1_SPEEDCTRL bit in the OMAP3 is an example.

Signed-off-by: Jonathan Solnit <jsolnit@gmail.com>

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arm926ejs: add NXP LPC32x0 cpu series support

This change adds initial support for NXP LPC32x0 SoC series.

Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud

arm926ejs: add NXP LPC32x0 cpu series support

This change adds initial support for NXP LPC32x0 SoC series.

Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Acked-by: Marek Vasut <marek.vasut@gmail.com>

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CMD: Fix CONFIG_CMD_SAVEBP_WRITE_SIZE -> CONFIG_CMD_SPL_WRITE_SIZE

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: scottwood@freescale.com

ARM926EJS: Fix cache.c to comply with checkpatch.pl

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>

ARM926EJS: Make asm routines volatile in cache ops

We certainly don't want the compiler to reorganise the code for dcache flushing.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sba

ARM926EJS: Make asm routines volatile in cache ops

We certainly don't want the compiler to reorganise the code for dcache flushing.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Acked-by: Mike Frysinger <vapier@gentoo.org>
Acked-by: Stefano Babic <sbabic@denx.de>

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ARM1136: MX35: Make asm routines volatile in cache ops

As well as pushed for ARM926EJS, we certainly don't want
the compiler to reorganise the code for dcache flushing
Fix checkpatch warnings as wel

ARM1136: MX35: Make asm routines volatile in cache ops

As well as pushed for ARM926EJS, we certainly don't want
the compiler to reorganise the code for dcache flushing
Fix checkpatch warnings as well.

Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Marek Vasut <marex@denx.de>
CC: Albert Aribaud <albert.u.boot@aribaud.net>

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ARM: add u-boot.imx as target for i.MX SOCs

Freescale SOCs require an header to u-boot.bin

The patch adds u-boot.imx to the default targets
if the imx file is set (IMX_CONFIG).

Signed-off-by: Stef

ARM: add u-boot.imx as target for i.MX SOCs

Freescale SOCs require an header to u-boot.bin

The patch adds u-boot.imx to the default targets
if the imx file is set (IMX_CONFIG).

Signed-off-by: Stefano Babic <sbabic@denx.de>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
CC: Loïc Minier <loic.minier@linaro.org>
CC: Mike Frysinger <vapier@gentoo.org>
Acked-by: Mike Frysinger <vapier@gentoo.org>
Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
Tested-by: Dirk Behme <dirk.behme@googlemail.com>

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DMA: Split the APBH DMA init into block and channel init

This fixes the issue where mxs_dma_init() was called either twice or never,
without introducing any new init hooks.

The idea is to allow eac

DMA: Split the APBH DMA init into block and channel init

This fixes the issue where mxs_dma_init() was called either twice or never,
without introducing any new init hooks.

The idea is to allow each and every device using the APBH DMA block to
configure and request only the channels it uses, instead of making it call init
for all the channels as is now.

The common DMA block init part, which only configures the block, is then called
from CPUs arch_cpu_init() call.

NOTE: This patch depends on:

http://patchwork.ozlabs.org/patch/150957/

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Detlev Zundel <dzu@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Tested-by: Fabio Estevam <fabio.estevam@freescale.com>

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ARM: 926ejs: use debug() for misaligned addresses

Misaligned warnings are useful to debug faulty drivers.
A misaligned warning is printed also when the driver
is correct - use debug() instead of pri

ARM: 926ejs: use debug() for misaligned addresses

Misaligned warnings are useful to debug faulty drivers.
A misaligned warning is printed also when the driver
is correct - use debug() instead of printf().

Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Albert Aribaud <albert.u.boot@aribaud.net>
CC: Mike Frysinger <vapier@gentoo.org>
CC: Marek Vasut <marex@denx.de>
Acked-by: Marek Vasut <marex@denx.de>

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ARM1136: add cache flush and invalidate operations

Since commit 5c1ad3e6f8ae578bbe30e09652f1531e9bc22031
(net: fec_mxc: allow use with cache enabled) the FEC_MXC
driver uses flush_dcache_range() and

ARM1136: add cache flush and invalidate operations

Since commit 5c1ad3e6f8ae578bbe30e09652f1531e9bc22031
(net: fec_mxc: allow use with cache enabled) the FEC_MXC
driver uses flush_dcache_range() and invalidate_dcache_range()
functions. This driver is also configured for ARM1136 based
'flea3' and 'mx35pdk' boards which currently do not build
as there are no ARM1136 specific flush_dcache_range() and
invalidate_dcache_range() functions. Add various ARM1136
cache functions to fix building for 'flea3' and 'mx35pdk'.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
Signed-off-by: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
CC: Mike Frysinger <vapier@gentoo.org>
CC: Marek Vasut <marex@denx.de>
Acked-by: Marek Vasut <marex@denx.de>

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i.MX6: implement enable_caches()

disabled by default until drivers are fixed

Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Acked-by: Marek Vasut <marex@denx.de>

arm: Use common .lds file where possible

Each cpu directory currently has its own .lds file. This is only needed
in most cases because the start.o file is in a different subdir.

Now that we can fac

arm: Use common .lds file where possible

Each cpu directory currently has its own .lds file. This is only needed
in most cases because the start.o file is in a different subdir.

Now that we can factor out this difference, we can move most cpus over
to the common .lds file.

Signed-off-by: Simon Glass <sjg@chromium.org>

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arm: add a common .lds link script

Most ARM CPUs use a very similar link script. This adds a basic
script that can be used by most CPUs.

Two new symbols are introduced which are intended to eventua

arm: add a common .lds link script

Most ARM CPUs use a very similar link script. This adds a basic
script that can be used by most CPUs.

Two new symbols are introduced which are intended to eventually be
defined on all architectures to make things easier for generic relocation
and reduce special-case code for each architecture:

__image_copy_start is the start of the text area (equivalent to the
existing _start on ARM). It marks the start of the region which must be
copied to a new location during relocation. This symbol is called
__text_start on x86 and microblaze.

__image_copy_end is the end of the region which must be copied to a new
location during relocation. It is normally equal to the start of the BSS
region, but this can vary in some cases (SPL?). Making this an explicit
symbol on its own removes any ambiguity and permits common code to always
do the right thing.

This new script makes use of CPUDIR, now defined by both Makefile and
spl/Makefile, to find the directory containing the start.o object file,
which is always placed first in the image.

To permit MMU setup prior to relocation (as used by pxa) we add an area
to the link script which contains space for this. This is taken
from commit 7f4cfcf. CPUs can put the contents in there using their
start.S file. BTW, shouldn't that area be 16KB-aligned?

Signed-off-by: Simon Glass <sjg@chromium.org>

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