| b736e4b9 | 10-Oct-2012 |
Stefano Babic <sbabic@denx.de> |
ARM: Fix start.S when used with SPL in arm1136
This patch modifies start.S for the arm1136 to make it
conform to start.S in armv7 architecture, to make it
usable if the SPL framework is used.
Sign
ARM: Fix start.S when used with SPL in arm1136
This patch modifies start.S for the arm1136 to make it
conform to start.S in armv7 architecture, to make it
usable if the SPL framework is used.
Signed-off-by: Stefano Babic <sbabic@denx.de>
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| 25164218 | 25-Oct-2012 |
Andrew Bradford <andrew@bradfordembedded.com> |
am33xx: Enable UART{1,2,3,4,5} clocks
If configured to use UART{1,2,3,4,5} such as on the Beaglebone RS232
cape or the am335x_evm daughterboard, enable the required clocks for
the UART in use.
Sign
am33xx: Enable UART{1,2,3,4,5} clocks
If configured to use UART{1,2,3,4,5} such as on the Beaglebone RS232
cape or the am335x_evm daughterboard, enable the required clocks for
the UART in use.
Signed-off-by: Andrew Bradford <andrew@bradfordembedded.com>
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| c00f69db | 18-Oct-2012 |
Peter Korsgaard <peter.korsgaard@barco.com> |
am33xx: support board specific ddr settings
Move the hardcoded ddr2/ddr3 settings for the ti boards to board code,
so other boards can use different types/timings.
Signed-off-by: Peter Korsgaard <p
am33xx: support board specific ddr settings
Move the hardcoded ddr2/ddr3 settings for the ti boards to board code,
so other boards can use different types/timings.
Signed-off-by: Peter Korsgaard <peter.korsgaard@barco.com>
[trini: Make apply with rtc32k_enable() in the file]
Signed-off-by: Tom Rini <trini@ti.com>
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| 000820b5 | 08-Mar-2012 |
Vaibhav Hiremath <hvaibhav@ti.com> |
am335x: Enable RTC 32K OSC clock
In order to support low power state, you must source kernel system
timers to persistent clock, available across suspend/resume. In case of
AM335x device, the only s
am335x: Enable RTC 32K OSC clock
In order to support low power state, you must source kernel system
timers to persistent clock, available across suspend/resume. In case of
AM335x device, the only source we have is, RTC32K, available in
wakeup/always-on domain. Having said that, during validation it has
been observed that, RTC clock need couple of seconds delay to stabilize
the RTC OSC clock; and such a huge delay is not acceptable in kernel
especially during early init and also it will impact quick/fast boot
use-cases.
So, RTC32k OSC enable dependency has been shifted to
SPL/first-bootloader.
Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
Signed-off-by: Tom Rini <trini@ti.com>
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| c4fe17f6 | 07-May-2012 |
Fabio Estevam <fabio.estevam@freescale.com> |
mx5: Add workaround for ARM erratum ID 468414
Add the software workaround for ARM erratum ID 468414.
According to mx53/mx51 errata document:
"ENGcm11133 - ARM: NEON load data can be incorrectly fo
mx5: Add workaround for ARM erratum ID 468414
Add the software workaround for ARM erratum ID 468414.
According to mx53/mx51 errata document:
"ENGcm11133 - ARM: NEON load data can be incorrectly forwarded to a
subsequent request
Description:
Under very specific set of conditions, data from a Neon load request can be incorrectly forwarded
to a subsequent, unrelated memory request.
The conditions are as follows:
• Neon loads and stores must be in use
• Neon L1 caching must be disabled
• Trustzone must be configured and in use
• The secure memory address space and the non-secure memory address space both use the same
physical addresses, either as an alias or the same memory location or for separate memory
locations
The issue is reported by ARM, erratum ID 468414, Category 2"
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
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| 782b0288 | 15-Oct-2012 |
Fabio Estevam <fabio.estevam@freescale.com> |
mx5: lowlevel_init.S: Fix PLL settings for mx53
Currently PLL2 is not explicitely configured for mx53 and it runs at 333MHz.
Since PLL2 is the parent clock for DDR2, IPU, VPU, we should set it at 4
mx5: lowlevel_init.S: Fix PLL settings for mx53
Currently PLL2 is not explicitely configured for mx53 and it runs at 333MHz.
Since PLL2 is the parent clock for DDR2, IPU, VPU, we should set it at 400MHz
instead.
Without doing so, it is not possible to use a 2.6.35 FSL kernel and display HDMI
at 1080p because the IPU clock cannot reach the requested frequency.
Set PLL2 to 400MHz, so that 1080p can be played and the DDR2 can run at its
maximum frequency.
Also, setup the other PLL's as done in FSL U-boot and re-arrange the code a little
bit to allow easier comparison with the original clock setup from FSL U-boot.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
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