ARM: OMAP5: clock: Add the prcm register changes required for ES2.0

PRCM register addresses are changed from ES1.0 to ES2.0 due to
PER power domain getting moved to CORE power domain.

So adding the

ARM: OMAP5: clock: Add the prcm register changes required for ES2.0

PRCM register addresses are changed from ES1.0 to ES2.0 due to
PER power domain getting moved to CORE power domain.

So adding the nessecary register changes for the same.

Signed-off-by: R Sricharan <r.sricharan@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
Cc: Tom Rini <trini@ti.com>

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ARM: OMAP5: Add silicon id support for ES2.0 revision.

Adding the CPU detection suport for OMAP5430 and
OMAP5432 ES2.0 SOCs.

Signed-off-by: R Sricharan <r.sricharan@ti.com>
Cc: Tom Rini <trini@ti.c

ARM: OMAP5: Add silicon id support for ES2.0 revision.

Adding the CPU detection suport for OMAP5430 and
OMAP5432 ES2.0 SOCs.

Signed-off-by: R Sricharan <r.sricharan@ti.com>
Cc: Tom Rini <trini@ti.com>
Cc: Nishanth Menon <nm@ti.com>

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ARM: OMAP5: Clean up iosettings code

There is some code duplication in the ddr io settings code.
This is avoided by moving the data to a Soc specific place and
letting the code generic.

This avoids

ARM: OMAP5: Clean up iosettings code

There is some code duplication in the ddr io settings code.
This is avoided by moving the data to a Soc specific place and
letting the code generic.

This avoids unnessecary code addition for future socs.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>

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ARM: OMAP4+: Make control module register structure generic

A seperate omap_sys_ctrl_regs structure is defined for
omap4 & 5. If there is any change in control module for
any of the ES versions, a n

ARM: OMAP4+: Make control module register structure generic

A seperate omap_sys_ctrl_regs structure is defined for
omap4 & 5. If there is any change in control module for
any of the ES versions, a new structure needs to be created.
In order to remove this dependency, making the register
structure generic for all the omap4+ boards.

Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>

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ARM: OMAP4+: Cleanup emif specific files

Removing the duplicated code in ddr3 initialization.
Also creating structure for lpddr2 mode registers to
avoid unnessecary revision checks.

These change re

ARM: OMAP4+: Cleanup emif specific files

Removing the duplicated code in ddr3 initialization.
Also creating structure for lpddr2 mode registers to
avoid unnessecary revision checks.

These change reduces code addition for future Socs.

Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>

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ARM: OMAP4+: Clean up the pmic code

The pmic code is duplicated for OMAP 4 and 5.
Instead move the data to Soc specific place and
share the code.

Signed-off-by: R Sricharan <r.sricharan@ti.com>
Sig

ARM: OMAP4+: Clean up the pmic code

The pmic code is duplicated for OMAP 4 and 5.
Instead move the data to Soc specific place and
share the code.

Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>

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ARM: OMAP4+: Cleanup the clocks layer

Currently there is quite a lot of code which
is duplicated in the clocks code for OMAP 4 and 5
Socs. Avoiding this here by moving the clocks
data to a SOC speci

ARM: OMAP4+: Cleanup the clocks layer

Currently there is quite a lot of code which
is duplicated in the clocks code for OMAP 4 and 5
Socs. Avoiding this here by moving the clocks
data to a SOC specific place and the sharing the
common code.

This helps in addition of a new Soc with minimal
changes.

Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>

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ARM: OMAP4+: Change the PRCM structure prototype common for all Socs

The current PRCM structure prototype directly matches the hardware
register layout. So there is a need to change this for every n

ARM: OMAP4+: Change the PRCM structure prototype common for all Socs

The current PRCM structure prototype directly matches the hardware
register layout. So there is a need to change this for every new silicon
revision which has register space changes.

Avoiding this by making the prototye generic and populating the register
addresses seperately for all Socs.

Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>

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ARM: OMAP4+: emif: Detect SDRAM from SDRAM config register

Now SDRAM initialization is done on the basis of omap revision.
Instead this should be done on basis of SDRAM type read from
EMIF_SDRAM_CON

ARM: OMAP4+: emif: Detect SDRAM from SDRAM config register

Now SDRAM initialization is done on the basis of omap revision.
Instead this should be done on basis of SDRAM type read from
EMIF_SDRAM_CONFIG register. This will be helpful to avoid
unnessecary cpu checks for new boards

Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>

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OMAP3: Initialize gpmc if SPL_ONENAND_SUPPORT is enabled.

In order to use SPL boot from OneNAND we should initialize the gpmc.

Signed-off-by: Enric Balletbo i Serra <eballetbo@iseebcn.com>

SPL: ONENAND: Fix some ONENAND related defines.

Some ONENAND related defines use the term ONE_NAND instead of
ONENAND, as the technology name is ONENAND this patch replaces
all these defines.

Signe

SPL: ONENAND: Fix some ONENAND related defines.

Some ONENAND related defines use the term ONE_NAND instead of
ONENAND, as the technology name is ONENAND this patch replaces
all these defines.

Signed-off-by: Enric Balletbo i Serra <eballetbo@iseebcn.com>

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omap_hsmmc: add driver check for write protection

Add check for write protection in omap mmc driver.

Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Signed-off-by: Igor Grinberg <grinberg@co

omap_hsmmc: add driver check for write protection

Add check for write protection in omap mmc driver.

Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
Reviewed-by: Tom Rini <trini@ti.com>

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omap_hsmmc: implement driver check for card detection

Implement driver check for card detection.

Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Signed-off-by: Igor Grinberg <grinberg@compul

omap_hsmmc: implement driver check for card detection

Implement driver check for card detection.

Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>

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am33xx: Update DDR3 EMIF configuration sequence

Based on
http://processors.wiki.ti.com/index.php/AM335x_EMIF_Configuration_tips
we need to re-work our sequence in config_sdram slightly to match what

am33xx: Update DDR3 EMIF configuration sequence

Based on
http://processors.wiki.ti.com/index.php/AM335x_EMIF_Configuration_tips
we need to re-work our sequence in config_sdram slightly to match what
the TRM describes as the correct sequence. In our current (incorrect)
sequence some edge cases may fail to initalize correctly.

Signed-off-by: Tom Rini <trini@ti.com>

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EXYNOS5: Add function to enable XXTI clock source

This patch adds funtion to enable XXTI clock source
required by MAX98095 codec.

Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Signed-

EXYNOS5: Add function to enable XXTI clock source

This patch adds funtion to enable XXTI clock source
required by MAX98095 codec.

Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>

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ARM: mx6: use common CPU errata config options

Now that U-Boot has common CONFIG_ options to work around some ARM CPU
errata, enable the relevant options on MX6, and remove the custom
lowlevel_init.

ARM: mx6: use common CPU errata config options

Now that U-Boot has common CONFIG_ options to work around some ARM CPU
errata, enable the relevant options on MX6, and remove the custom
lowlevel_init.S, since it's just duplicated code now.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Jason Liu <r64343@freescale.com>

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mxs: timrot: Rename local macros

Local macros apply to both iMX23 and iMX28. This patch renames local
macros with attribute MX28 to MXS.

Signed-off-by: Fadil Berisha <f.koliqi@gmail.com>
Cc: Marek

mxs: timrot: Rename local macros

Local macros apply to both iMX23 and iMX28. This patch renames local
macros with attribute MX28 to MXS.

Signed-off-by: Fadil Berisha <f.koliqi@gmail.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>

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mxs: timrot: Add support to i.MX23

This patch add timer support to i.MX23 and complete bit fields and values
on regs-timrot.h.
Testet on imx23-olinuxino board.

Signed-off-by: Fadil Berisha <f.koliq

mxs: timrot: Add support to i.MX23

This patch add timer support to i.MX23 and complete bit fields and values
on regs-timrot.h.
Testet on imx23-olinuxino board.

Signed-off-by: Fadil Berisha <f.koliqi@gmail.com>
Acked-by: Marek Vasut <marex@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Acked-by: Otavio Salvador <otavio@ossystems.com.br>

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mx23: Document the tRAS lockout setting in memory initialization

Add a comment about the tRAS lockout setting of HW_DRAM_CTL08 to
enable the 'Fast Auto Pre-Charge' found in the memory chip. The
sett

mx23: Document the tRAS lockout setting in memory initialization

Add a comment about the tRAS lockout setting of HW_DRAM_CTL08 to
enable the 'Fast Auto Pre-Charge' found in the memory chip. The
setting is applied after memory initialization and it is worth
document it.

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>

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mxs: Rename CONFIG_SPL_MX28_PSWITCH_WAIT to CONFIG_SPL_MXS_PSWITCH_WAIT

The power switch option is compatible with i.MX23 and i.MX28 so the
configration option needs to reflect it. We choose
'CONFIG

mxs: Rename CONFIG_SPL_MX28_PSWITCH_WAIT to CONFIG_SPL_MXS_PSWITCH_WAIT

The power switch option is compatible with i.MX23 and i.MX28 so the
configration option needs to reflect it. We choose
'CONFIG_SPL_MXS_PSWITCH_WAIT' for the option name.

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Acked-by: Marek Vasut <marex@denx.de>

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mxs: mmc: spi: dma: Better wrap the MXS differences

This patch streamlines the differences between the MX23 and MX28 by
implementing a few helper functions to handle different DMA channel
mapping, d

mxs: mmc: spi: dma: Better wrap the MXS differences

This patch streamlines the differences between the MX23 and MX28 by
implementing a few helper functions to handle different DMA channel
mapping, different clock domain for SSP block and fixes a few minor
bugs.

First of all, the DMA channel mapping is now fixed in dma.h by defining
the actual channel map for both MX23 and MX28. Thus, MX23 now does no
longer use MX28 channel map which was wrong. Also, there is a fix for
MX28 DMA channel map, where the last four channels were incorrect.

Next, because correct DMA channel map is in place, the mxs_dma_init_channel()
call now bases the channel ID starting from SSP port #0. This removes the
need for DMA channel offset being added and cleans up the code. For the
same reason, the SSP0 offset can now be used in mxs_dma_desc_append(), thus
no need to adjust dma channel number in the driver either.

Lastly, the SSP clock ID is now retrieved by calling mxs_ssp_clock_by_bus()
which handles the fact that MX23 has shared SSP clock for both ports, while
MX28 has per-port SSP clock.

Finally, the mxs_ssp_bus_id_valid() pulls out two implementations of the
same functionality from MMC and SPI driver into common code.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Stefano Babic <sbabic@denx.de>

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mxs: Reset the EMI block on mx23

The real reason for memory instability was the fact that the EMI block
was gated and not reset throughout the boards' operation. This patch
resets the EMI block prop

mxs: Reset the EMI block on mx23

The real reason for memory instability was the fact that the EMI block
was gated and not reset throughout the boards' operation. This patch
resets the EMI block properly while also reverts the memory voltage bump.
The memory stability issues were caused by the EMI not being reset properly
and thus there is no longer need to run the memory at higher voltage than
it ought to run at.

This partly reverts 8303ed128a55519f19c5f11087032d4bc4e0537a .

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Stefano Babic <sbabic@denx.de>

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Merge branch 'master' of git://git.denx.de/u-boot-arm

Merge branch 'u-boot-ti/master' into 'u-boot-arm/master'

Merge 'u-boot-microblaze/mainline/arm' into 'u-boot-arm/master'

This pulls the three following ZYNQ commits into ARM master:

7dca54f8: xilinx: zynq: Enable DCC and create new zynq_dcc board
59c651f

Merge 'u-boot-microblaze/mainline/arm' into 'u-boot-arm/master'

This pulls the three following ZYNQ commits into ARM master:

7dca54f8: xilinx: zynq: Enable DCC and create new zynq_dcc board
59c651f4: arm: zynq: Add SLCR support with system reset
00ed3458: arm: zynq: Add lowlevel initialization to C

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