| 6247c465 | 14-Jun-2013 |
trem <tremyfr@yahoo.fr> |
mx27: add function enable_caches
Signed-off-by: Philippe Reynes <tremyfr@yahoo.fr> |
| ca35a0cd | 11-Jun-2013 |
Simon Glass <sjg@chromium.org> |
exynos: Avoid function instrumentation for microsecond timer
For tracing to work it has to be able to access the microsecond timer without causing a recursive call to the function entry/exit handler
exynos: Avoid function instrumentation for microsecond timer
For tracing to work it has to be able to access the microsecond timer without causing a recursive call to the function entry/exit handlers. Add attributes to the relevant functions to support this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
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| 84c617be | 21-Jun-2013 |
Mike Dunn <mikedunn@newsguy.com> |
pxa: use -mcpu=xscale compiler option
Pass '-mcpu=xscale' to the compiler instead of march and mtune. This will cause gcc to define the __XSCALE__ macro.
Signed-off-by: Mike Dunn <mikedunn@newsguy
pxa: use -mcpu=xscale compiler option
Pass '-mcpu=xscale' to the compiler instead of march and mtune. This will cause gcc to define the __XSCALE__ macro.
Signed-off-by: Mike Dunn <mikedunn@newsguy.com>
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| 097d86d0 | 17-Jun-2013 |
Mike Dunn <mikedunn@newsguy.com> |
pxa: turn icache off in cpu_init_crit()
The comment in the low-level initialization function cpu_init_crit() says that the caches are being disabled, but (oddly) the icache is actually turned on. Th
pxa: turn icache off in cpu_init_crit()
The comment in the low-level initialization function cpu_init_crit() says that the caches are being disabled, but (oddly) the icache is actually turned on. This is probably not a good idea prior to relocating code, so this patch turns it off. Tested on the pxa270.
Signed-off-by: Mike Dunn <mikedunn@newsguy.com>
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| 47bd65ef | 11-Jun-2013 |
Albert ARIBAUD <albert.u.boot@aribaud.net> |
arm: make __rel_dyn_{start, end} compiler-generated
This change is only done where needed: some linker scripts may contain relocation symbols yet remain unchanged.
__rel_dyn_start and __rel_dyn_end
arm: make __rel_dyn_{start, end} compiler-generated
This change is only done where needed: some linker scripts may contain relocation symbols yet remain unchanged.
__rel_dyn_start and __rel_dyn_end each requires its own output section; putting them in relocation sections changes their flags and breaks relocation.
Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net> Tested-by: Lubomir Popov <lpopov@mm-sol.com> Tested-by: Jeroen Hofstee <jeroen@myspectrum.nl> Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
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| d026dec8 | 11-Jun-2013 |
Albert ARIBAUD <albert.u.boot@aribaud.net> |
arm: make __image_copy_{start, end} compiler-generated
This change is only done where needed: some linker scripts may contain __image_copy_{start,end} yet remain unchanged.
Also, __image_copy_end n
arm: make __image_copy_{start, end} compiler-generated
This change is only done where needed: some linker scripts may contain __image_copy_{start,end} yet remain unchanged.
Also, __image_copy_end needs its own section; putting it in relocation sections changes their flags and makes relocation break.
Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net> Tested-by: Lubomir Popov <lpopov@mm-sol.com> Tested-by: Jeroen Hofstee <jeroen@myspectrum.nl> Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
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| 09d81184 | 11-Jun-2013 |
Albert ARIBAUD <albert.u.boot@aribaud.net> |
remove all references to .dynsym
Discard all .dynsym sections from linker scripts Remove all __dynsym_start definitions from linker scripts Remove all __dynsym_start references from the codebase
No
remove all references to .dynsym
Discard all .dynsym sections from linker scripts Remove all __dynsym_start definitions from linker scripts Remove all __dynsym_start references from the codebase
Note: this touches include/asm-generic/sections.h, which is not ARM-specific, but actual uses of __dynsym_start are only in ARM, so this patch can safely go through the ARM repository.
Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net> Tested-by: Lubomir Popov <lpopov@mm-sol.com> Tested-by: Jeroen Hofstee <jeroen@myspectrum.nl> Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
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| c2543a21 | 19-Jun-2013 |
Albert ARIBAUD <albert.u.boot@aribaud.net> |
Merge branch 'u-boot-ti/master' into 'u-boot-arm/master' |
| 69f14dc2 | 19-Jun-2013 |
Albert ARIBAUD <albert.u.boot@aribaud.net> |
Merge branch 'u-boot-samsung/master' into 'u-boot-arm/master'
Conflicts: spl/Makefile |
| 7ea7f689 | 04-Jun-2013 |
Heiko Schocher <hs@denx.de> |
arm, am33xx: move uart soft reset code to common place
move uart soft reset code to common place and call this function from board code, instead of copy and paste this code for every board.
Signed-
arm, am33xx: move uart soft reset code to common place
move uart soft reset code to common place and call this function from board code, instead of copy and paste this code for every board.
Signed-off-by: Heiko Schocher <hs@denx.de> Cc: Matt Porter <mporter@ti.com> Cc: Lars Poeschel <poeschel@lemonage.de> Cc: Tom Rini <trini@ti.com> Cc: Enric Balletbo i Serra <eballetbo@iseebcn.com> Acked-by: Tom Rini <trini@ti.com> [trini: Fix igep0033 build, remove 'regval' on pcm051] Signed-off-by: Tom Rini <trini@ti.com>
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| 7b9c5d0b | 04-Jun-2013 |
Heiko Schocher <hs@denx.de> |
arm, am335x: make mpu pll config configurable
upcoming support for siemens boards switches mpu pll clk in board code. So make this configurable.
Signed-off-by: Heiko Schocher <hs@denx.de> Cc: Tom R
arm, am335x: make mpu pll config configurable
upcoming support for siemens boards switches mpu pll clk in board code. So make this configurable.
Signed-off-by: Heiko Schocher <hs@denx.de> Cc: Tom Rini <trini@ti.com>
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| 49f78365 | 05-Jun-2013 |
Heiko Schocher <hs@denx.de> |
arm, am33xx: move rtc32k_enable() to common place
move rtc32k_enable() to common place so all am33xx boards can use it.
Signed-off-by: Heiko Schocher <hs@denx.de> Cc: Matt Porter <mporter@ti.com> C
arm, am33xx: move rtc32k_enable() to common place
move rtc32k_enable() to common place so all am33xx boards can use it.
Signed-off-by: Heiko Schocher <hs@denx.de> Cc: Matt Porter <mporter@ti.com> Cc: Lars Poeschel <poeschel@lemonage.de> Cc: Tom Rini <trini@ti.com> Cc: Enric Balletbo i Serra <eballetbo@iseebcn.com>
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| 2b81c26b | 27-Apr-2013 |
Amar <amarendra.xt@samsung.com> |
EXYNOS5: DWMMC: Initialise the local variable to avoid unwanted results.
This patch initialises the local variable 'shift' to zero. The uninitialised local variable 'shift' had garbage value and was
EXYNOS5: DWMMC: Initialise the local variable to avoid unwanted results.
This patch initialises the local variable 'shift' to zero. The uninitialised local variable 'shift' had garbage value and was resulting in unwnated results in the functions exynos5_get_mmc_clk() and exynos4_get_mmc_clk().
Signed-off-by: Amar <amarendra.xt@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Acked-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
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| 847e6693 | 21-May-2013 |
Sergey Yanovich <ynvich@gmail.com> |
arm: pxa: config option for PXA270 turbo mode
PXA270 CPU has turbo mode. The mode is 2.5 times faster than the default run mode. Activating the mode early significantly speeds up boot process.
Sign
arm: pxa: config option for PXA270 turbo mode
PXA270 CPU has turbo mode. The mode is 2.5 times faster than the default run mode. Activating the mode early significantly speeds up boot process.
Signed-off-by: Sergey Yanovich <ynvich@gmail.com>
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| 68cd4a4c | 29-May-2013 |
Vishwanathrao Badarkhe, Manish <manishv.b@ti.com> |
arm: da830: moved pinmux configurations to the arch tree
Move pinmux configurations for the DA830 SoCs from board file to the arch tree so that it can be used for all da830 based devices. Also, avoi
arm: da830: moved pinmux configurations to the arch tree
Move pinmux configurations for the DA830 SoCs from board file to the arch tree so that it can be used for all da830 based devices. Also, avoids duplicate pinmuxing in case of NAND.
Signed-off-by: Vishwanathrao Badarkhe, Manish <manishv.b@ti.com> Reviewed-by: Tom Rini <trini@ti.com> Acked-by: Christian Riesch <christian.riesch@omicron.at>
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| ee28edac | 15-May-2013 |
Lubomir Popov <lpopov@mm-sol.com> |
OMAP5: Enable access to auxclk registers
auxclk0 and auxclk1 are utilized on some OMAP5 boards. Define the infrastructure needed for accessing them without using magic numbers.
Also remove unrelate
OMAP5: Enable access to auxclk registers
auxclk0 and auxclk1 are utilized on some OMAP5 boards. Define the infrastructure needed for accessing them without using magic numbers.
Also remove unrelated TPS62361 defines from clocks.h
Signed-off-by: Lubomir Popov <lpopov@mm-sol.com>
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| 7f5eef93 | 04-Jun-2013 |
Tom Rini <trini@ti.com> |
arm: Remove OMAP2420H4 and all omap24xx support
The omap2420H4 was the only mainline omap24xx board. Prior to being fixed by Jon Hunter in time for v2013.04 it had been functionally broken for a ve
arm: Remove OMAP2420H4 and all omap24xx support
The omap2420H4 was the only mainline omap24xx board. Prior to being fixed by Jon Hunter in time for v2013.04 it had been functionally broken for a very long time. Remove this board as there's not been interest in it in U-Boot for quite a long time.
Signed-off-by: Tom Rini <trini@ti.com>
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| 92b0482c | 30-May-2013 |
Sricharan R <r.sricharan@ti.com> |
ARM: DRA7xx: EMIF: Change settings required for EVM board
DRA7 EVM board has the below configuration. Adding the settings for the same here.
2Gb_1_35V_DDR3L part * 2 on EMIF1 2Gb_1_35V_DDR3L
ARM: DRA7xx: EMIF: Change settings required for EVM board
DRA7 EVM board has the below configuration. Adding the settings for the same here.
2Gb_1_35V_DDR3L part * 2 on EMIF1 2Gb_1_35V_DDR3L part * 4 on EMIF2
Signed-off-by: Sricharan R <r.sricharan@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
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| 97405d84 | 30-May-2013 |
Lokesh Vutla <lokeshvutla@ti.com> |
ARM: DRA7xx: clocks: Update PLL values
Update PLL values. SYS_CLKSEL value for 20MHz is changed to 2. In other platforms SYS_CLKSEL value 2 represents reserved. But in sys_clk array ind 1 is used fo
ARM: DRA7xx: clocks: Update PLL values
Update PLL values. SYS_CLKSEL value for 20MHz is changed to 2. In other platforms SYS_CLKSEL value 2 represents reserved. But in sys_clk array ind 1 is used for 13Mhz. Since other platforms are not using 13Mhz, reusing index 1 for 20MHz.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Sricharan R <r.sricharan@ti.com>
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| f9b814a8 | 30-May-2013 |
Sricharan R <r.sricharan@ti.com> |
ARM: DRA7xx: Correct the SYS_CLK to 20MHZ
The sys_clk on the dra evm board is 20MHZ. Changing the configuration for the same. And also moving V_SCLK, V_OSCK defines to arch/clock.h for OMAP4+ boards
ARM: DRA7xx: Correct the SYS_CLK to 20MHZ
The sys_clk on the dra evm board is 20MHZ. Changing the configuration for the same. And also moving V_SCLK, V_OSCK defines to arch/clock.h for OMAP4+ boards.
Signed-off-by: Sricharan R <r.sricharan@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
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| e9d6cd04 | 30-May-2013 |
Lokesh Vutla <lokeshvutla@ti.com> |
ARM: DRA7xx: Do not enable srcomp for DRA7xx Soc's
Slew rate compensation cells are not present for DRA7xx Soc's. So return from function srcomp_enable() if soc is not OMAP54xx.
Signed-off-by: Loke
ARM: DRA7xx: Do not enable srcomp for DRA7xx Soc's
Slew rate compensation cells are not present for DRA7xx Soc's. So return from function srcomp_enable() if soc is not OMAP54xx.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
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| 18c9d55a | 30-May-2013 |
Nishanth Menon <nm@ti.com> |
ARM: OMAP5: DRA7xx: support class 0 optimized voltages
DRA752 now uses AVS Class 0 voltages which are voltages in efuse.
This means that we can now use the optimized voltages which are stored as mV
ARM: OMAP5: DRA7xx: support class 0 optimized voltages
DRA752 now uses AVS Class 0 voltages which are voltages in efuse.
This means that we can now use the optimized voltages which are stored as mV values in efuse and program PMIC accordingly.
This allows us to go with higher OPP as needed in the system without the need for implementing complex AVS logic.
Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
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| 3332b244 | 30-May-2013 |
Lokesh Vutla <lokeshvutla@ti.com> |
ARM: DRA7xx: clocks: Fixing i2c_init for PMIC
In DRA7xx Soc's voltage scaling is done using GPI2C. So i2c_init should happen before scaling. I2C driver uses __udelay which needs timer to be initiali
ARM: DRA7xx: clocks: Fixing i2c_init for PMIC
In DRA7xx Soc's voltage scaling is done using GPI2C. So i2c_init should happen before scaling. I2C driver uses __udelay which needs timer to be initialized. So moving timer_init just before voltage scaling. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
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| 63fc0c77 | 30-May-2013 |
Lokesh Vutla <lokeshvutla@ti.com> |
ARM: DRA7xx: power Add support for tps659038 PMIC
TPS659038 is the power IC used in DRA7XX boards. Adding support for this and also adding pmic data for DRA7XX boards.
Signed-off-by: Lokesh Vutla <
ARM: DRA7xx: power Add support for tps659038 PMIC
TPS659038 is the power IC used in DRA7XX boards. Adding support for this and also adding pmic data for DRA7XX boards.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
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| 4ca94d81 | 30-May-2013 |
Lokesh Vutla <lokeshvutla@ti.com> |
ARM: OMAP4+: pmic: Make generic bus init and write functions
Voltage scaling can be done in two ways: -> Using SR I2C -> Using GP I2C In order to support both, have a function pointer in pmic_data s
ARM: OMAP4+: pmic: Make generic bus init and write functions
Voltage scaling can be done in two ways: -> Using SR I2C -> Using GP I2C In order to support both, have a function pointer in pmic_data so that we can call as per our requirement.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
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