| bb14469a | 22-Apr-2014 |
Stephen Warren <swarren@nvidia.com> |
ARM: tegra: add function to enable input clamping on tristate
The HW-defined procedure for booting Tegra requires that
CLAMP_INPUTS_WHEN_TRISTATED be enabled before programming the pinmux.
Add a fun
ARM: tegra: add function to enable input clamping on tristate
The HW-defined procedure for booting Tegra requires that
CLAMP_INPUTS_WHEN_TRISTATED be enabled before programming the pinmux.
Add a function to the pinmux driver to allow boards to do this.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
show more ...
|
| 4a68d343 | 22-Apr-2014 |
Stephen Warren <swarren@nvidia.com> |
ARM: tegra: allow pinmux mux option not to be set by init tables
Define enum PMUX_FUNC_DEFAULT, which indicates that a table entry passed
to pinmux_config_pingrp()/pinmux_config_pingrp_table() shoul
ARM: tegra: allow pinmux mux option not to be set by init tables
Define enum PMUX_FUNC_DEFAULT, which indicates that a table entry passed
to pinmux_config_pingrp()/pinmux_config_pingrp_table() shouldn't change
the mux option in HW.
For pins that will be used as GPIOs, the mux option is irrelevant, so we
simply don't want to define any mux option in the pinmux initialization
table.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
show more ...
|
| 48ec7a94 | 21-Apr-2014 |
Stephen Warren <swarren@nvidia.com> |
ARM: tegra: fix CPU VDD comment in Tegra30 CPU init code
The register writes performed by arch/arm/cpu/arm720t/tegra30/cpu.c
enable_cpu_power_rail() set the voltage to 1.0V not 1.4V as the comment
i
ARM: tegra: fix CPU VDD comment in Tegra30 CPU init code
The register writes performed by arch/arm/cpu/arm720t/tegra30/cpu.c
enable_cpu_power_rail() set the voltage to 1.0V not 1.4V as the comment
implies. Fix the comment.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
show more ...
|
| f6ae1ca0 | 13-May-2014 |
Akshay Saraswat <akshay.s@samsung.com> |
S5P: Exynos: Add GPIO pin numbering and rename definitions
This patch includes following changes :
* Adds gpio pin numbering support for EXYNOS SOCs.
To have consistent 0..n-1 GPIO numbering the b
S5P: Exynos: Add GPIO pin numbering and rename definitions
This patch includes following changes :
* Adds gpio pin numbering support for EXYNOS SOCs.
To have consistent 0..n-1 GPIO numbering the banks are divided
into different parts where ever they have holes in them.
* Rename GPIO definitions from GPIO_... to S5P_GPIO_...
These changes were done to enable cmd_gpio for EXYNOS and
cmd_gpio has GPIO_INPUT same as s5p_gpio driver and hence
getting a error during compilation.
* Adds support for name to gpio conversion in s5p_gpio to enable
gpio command EXYNOS SoCs. Function has been added to asm/gpio.h
to decode the input gpio name to gpio number.
Example: SMDK5420 # gpio set gpa00
Signed-off-by: Leela Krishna Amudala <l.krishna@samsung.com>
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Acked-by: Przemyslaw Marczak <p.marczak@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
show more ...
|
| d2a3e911 | 09-May-2014 |
Albert ARIBAUD <albert.u.boot@aribaud.net> |
Merge branch 'u-boot/master'
Conflicts:
drivers/net/Makefile
(trivial merge) |
| 73ff6801 | 28-Mar-2014 |
Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> |
arm: rmobile: Update print_cpuinfo function
The print_cpuinfo fucntion has same code.
It has a code of many common. This adds a table of CPU information, duplicate
using for-loop.
Signed-off-by: N
arm: rmobile: Update print_cpuinfo function
The print_cpuinfo fucntion has same code.
It has a code of many common. This adds a table of CPU information, duplicate
using for-loop.
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
show more ...
|
| a028abea | 28-Mar-2014 |
Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> |
arm: rmobile: Add rmobile_get_cpu_rev_fraction() for R-Car SoCs
This adds rmobile_get_cpu_rev_fraction to get fraction revision for R-Car SoCs.
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.y
arm: rmobile: Add rmobile_get_cpu_rev_fraction() for R-Car SoCs
This adds rmobile_get_cpu_rev_fraction to get fraction revision for R-Car SoCs.
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
show more ...
|
| 210f7b2d | 28-Mar-2014 |
Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> |
arm: rmobile: Add 1 to value of the CPU revision in rmobile_get_cpu_rev_integer()
Value that can be obtained in the rmobile_get_cpu_rev_integer() starts at 0.
However, revisions to start from 1, whi
arm: rmobile: Add 1 to value of the CPU revision in rmobile_get_cpu_rev_integer()
Value that can be obtained in the rmobile_get_cpu_rev_integer() starts at 0.
However, revisions to start from 1, which adds 1.
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
show more ...
|
| 9b7fa2fe | 28-Mar-2014 |
Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> |
arm: rmobile: Merge functions to get the CPU information of R8A7790 and R8A7791
Functions to get the CPU information of R8A7790 and R8A7791 are common.
This merges these as cpu_info-rcar.c.
Signed-
arm: rmobile: Merge functions to get the CPU information of R8A7790 and R8A7791
Functions to get the CPU information of R8A7790 and R8A7791 are common.
This merges these as cpu_info-rcar.c.
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
show more ...
|
| 42c53ab0 | 28-Mar-2014 |
Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> |
arm: rmobile: r8a779x: Fix L2 cache init and latency setting
L2CTLR only need to update for cluster 0.
This changes L2CTLR to initialize only when cluster is 0.
Signed-off-by: Nobuhiro Iwamatsu <no
arm: rmobile: r8a779x: Fix L2 cache init and latency setting
L2CTLR only need to update for cluster 0.
This changes L2CTLR to initialize only when cluster is 0.
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
show more ...
|
| c9aab0f9 | 21-Apr-2014 |
Albert ARIBAUD <albert.u.boot@aribaud.net> |
Merge branch 'u-boot-ti/master' into 'u-boot-arm/master' |
| b149c4c3 | 18-Apr-2014 |
Tom Rini <trini@ti.com> |
ARM:tegra20: Remove aes debug prints
In 6e7b9f4 some of the debug prints for AES code moved into the generic
code, so we remove these additional calls.
Signed-off-by: Tom Rini <trini@ti.com>
Acked-
ARM:tegra20: Remove aes debug prints
In 6e7b9f4 some of the debug prints for AES code moved into the generic
code, so we remove these additional calls.
Signed-off-by: Tom Rini <trini@ti.com>
Acked-by: Tom Warren <twarren@nvidia.com>
show more ...
|
| 53eb768d | 18-Apr-2014 |
Stephen Warren <swarren@nvidia.com> |
aes: make apply_cbc_chain_data non-static
Tegra's crypto.c uses apply_cbc_chain_data() to sign the warm restart
code. This function was recently moved into the core aes.c and made
static, which prev
aes: make apply_cbc_chain_data non-static
Tegra's crypto.c uses apply_cbc_chain_data() to sign the warm restart
code. This function was recently moved into the core aes.c and made
static, which prevents the Tegra code from compiling. Make it public
again to avoid the compile errors:
arch/arm/cpu/tegra20-common/crypto.c: In function ‘sign_object’:
arch/arm/cpu/tegra20-common/crypto.c:74:3: warning: implicit declaration of function ‘apply_cbc_chain_data’ [-Wimplicit-function-declaration]
arch/arm/cpu/built-in.o: In function `sign_object':
.../arch/arm/cpu/tegra20-common/crypto.c:74: undefined reference to `apply_cbc_chain_data'
.../arch/arm/cpu/tegra20-common/crypto.c:78: undefined reference to `apply_cbc_chain_data'
Fixes: 6e7b9f4fa0ae ("aes: Move the AES-128-CBC encryption function to common code")
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Marek Vasut <marex@denx.de>
show more ...
|
| d8d7cbd9 | 31-Mar-2014 |
Masahiro Yamada <yamada.m@jp.panasonic.com> |
kbuild: use boolean macros to select tegra*-common directory
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> |
| 893b92f8 | 11-Apr-2014 |
Manish Badarkhe <badarkhe.manish@gmail.com> |
arm, da850: staticize funtions
Make funtions static which are locally used in file
and remove the declaration from header file.
Signed-off-by: Manish Badarkhe <badarkhe.manish@gmail.com> |
| d0e6d34d | 09-Apr-2014 |
Tom Rini <trini@ti.com> |
am335x: Switch to CONFIG_SKIP_LOWLEVEL_INIT from guarding SPL or NOR_BOOT
In the case of SPL or NOR_BOOT (no SPL involved) we need to include
certain code in the build. Use !CONFIG_SKIP_LOWLEVEL_IN
am335x: Switch to CONFIG_SKIP_LOWLEVEL_INIT from guarding SPL or NOR_BOOT
In the case of SPL or NOR_BOOT (no SPL involved) we need to include
certain code in the build. Use !CONFIG_SKIP_LOWLEVEL_INIT rather than
CONFIG_SPL_BUILD || CONFIG_NOR_BOOT to make the code clearer, and to
make supporting XIP QSPI boot clearer in the code.
Signed-off-by: Tom Rini <trini@ti.com>
Reviewed-by: Wolfgang Denk <wd@denx.de>
show more ...
|
| 30fe8c15 | 01-Apr-2014 |
Vitaly Andrianov <vitalya@ti.com> |
keystone2: add keystone multicore navigator driver
Multicore navigator consists of Network Coprocessor (NetCP) and
Queue Manager sub system. More details on the hardware can
be obtained from the fol
keystone2: add keystone multicore navigator driver
Multicore navigator consists of Network Coprocessor (NetCP) and
Queue Manager sub system. More details on the hardware can
be obtained from the following links:-
Network Coprocessor: http://www.ti.com/lit/pdf/sprugz6
Multicore Navigator: http://www.ti.com/lit/pdf/sprugr9
Multicore navigator driver implements APIs to configure
the Queue Manager and NetCP Pkt DMA.
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: WingMan Kwok <w-kwok2@ti.com>
Acked-by: Tom Rini <trini@ti.com>
show more ...
|
| ef509b90 | 04-Apr-2014 |
Vitaly Andrianov <vitalya@ti.com> |
k2hk: add support for k2hk SOC and EVM
k2hk EVM is based on Texas Instruments Keystone2 Hawking/Kepler
SoC. Keystone2 SoC has ARM v7 Cortex-A15 MPCore processor. Please
refer the ti/k2hk_evm/README
k2hk: add support for k2hk SOC and EVM
k2hk EVM is based on Texas Instruments Keystone2 Hawking/Kepler
SoC. Keystone2 SoC has ARM v7 Cortex-A15 MPCore processor. Please
refer the ti/k2hk_evm/README for details on the board, build and other
information.
This patch add support for keystone architecture and k2hk evm.
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: WingMan Kwok <w-kwok2@ti.com>
Signed-off-by: Sandeep Nair <sandeep_n@ti.com>
show more ...
|
| e8459dcc | 04-Apr-2014 |
Vitaly Andrianov <vitalya@ti.com> |
i2c, davinci: convert driver to new mutlibus/mutliadapter framework
- add davinci driver to new multibus/multiadpater support
- adapted all config files, which uses this driver
Signed-off-b
i2c, davinci: convert driver to new mutlibus/mutliadapter framework
- add davinci driver to new multibus/multiadpater support
- adapted all config files, which uses this driver
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Acked-by: Heiko Schocher <hs@denx.de>
show more ...
|
| 11bc7557 | 04-Apr-2014 |
Vitaly Andrianov <vitalya@ti.com> |
arm: add support for arch timer
This patch add basic support for the architecture timer found on recent
ARMv7 based SoCs.
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Murali Kari
arm: add support for arch timer
This patch add basic support for the architecture timer found on recent
ARMv7 based SoCs.
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
show more ...
|
| 79b079f3 | 03-Apr-2014 |
Tom Rini <trini@ti.com> |
dra7xx_evm: Add QSPI_4 support, qspiboot build target
We previously only supported QSPI_1 (single) support. Add QSPI_4 (quad)
read support as well. This means we can be given one of two boot devic
dra7xx_evm: Add QSPI_4 support, qspiboot build target
We previously only supported QSPI_1 (single) support. Add QSPI_4 (quad)
read support as well. This means we can be given one of two boot device
values, but don't care which it is, so perform a fixup on the QSPI_4
value. We add a qspiboot build target to better show how you would use
QSPI as a boot device in deployment. When we boot from QSPI, we can
check the environment for 'boot_os' to control Falcon Mode.
Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
Signed-off-by: Tom Rini <trini@ti.com>
show more ...
|
| 79e7e87f | 28-Mar-2014 |
Nishanth Menon <nm@ti.com> |
omap3/sys_info: provide interface to read die id
introduce get_die_id() function which allows generation of
information such as fake MAC address from the processor ID code.
Signed-off-by: Nishanth
omap3/sys_info: provide interface to read die id
introduce get_die_id() function which allows generation of
information such as fake MAC address from the processor ID code.
Signed-off-by: Nishanth Menon <nm@ti.com>
show more ...
|
| 8a0c6d6f | 28-Mar-2014 |
Nishanth Menon <nm@ti.com> |
OMAP: common: consolidate fake USB ethernet MAC address creation
TI platforms such as OMAP5uevm, PandaBoard, use equivalent
logic to generate fake USB MAC address from device unique DIE ID.
Consoli
OMAP: common: consolidate fake USB ethernet MAC address creation
TI platforms such as OMAP5uevm, PandaBoard, use equivalent
logic to generate fake USB MAC address from device unique DIE ID.
Consolidate this to a generic location such that other TI platforms such
as BeagleBoard-XM can also use the same.
NOTE: at this point in time, I dont yet see a need for a generic dummy
ethernet MAC address creation function, but if there is a need in the
future, this can be further abstracted out.
Signed-off-by: Nishanth Menon <nm@ti.com>
show more ...
|
| a88e55c4 | 25-Mar-2014 |
Wolfgang Denk <wd@denx.de> |
ARM: OMAP: replace custom sr32() by standard I/O accessors
Replace the custom bit manipulation function sr32() by standard I/O
accessors. A major motivation for this cleanup was the fact, that a
nu
ARM: OMAP: replace custom sr32() by standard I/O accessors
Replace the custom bit manipulation function sr32() by standard I/O
accessors. A major motivation for this cleanup was the fact, that a
number of calls of that function resulted in 32 bit wide shift
operations on u32 data, which according to the C-ISO/IEC-9899-Standard
provokes undefined behaviour:
6.5.7 Bitwise shift operators
...
If the value of the right operand is negative or is greater
than or equal to the width of the promoted left operand, the
behavior is undefined.
Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Tom Rini <trini@ti.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
show more ...
|
| 4e468502 | 25-Mar-2014 |
Wolfgang Denk <wd@denx.de> |
ARM: OMAP: hide custom bit manipulation function sr32()
The only remaining user of the custom bit manipulation function sr32()
is arch/arm/cpu/armv7/omap3/clock.c, so make it a static function in
t
ARM: OMAP: hide custom bit manipulation function sr32()
The only remaining user of the custom bit manipulation function sr32()
is arch/arm/cpu/armv7/omap3/clock.c, so make it a static function in
that file to prepare complete removal.
Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Tom Rini <trini@ti.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
show more ...
|