| 34584d19 | 16-Oct-2014 |
Marek Vasut <marex@denx.de> |
arm: socfpga: Zap spl.h and ad-hoc related syms
Switch to the common spl.h file and zap the arch/spl.h . Since the arch/spl.h contained various ad-hoc symbols, zap those symbols as well and rework t
arm: socfpga: Zap spl.h and ad-hoc related syms
Switch to the common spl.h file and zap the arch/spl.h . Since the arch/spl.h contained various ad-hoc symbols, zap those symbols as well and rework the board configuration a little so it doesn't depend on them.
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Vince Bridgers <vbridger@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Acked-by: Pavel Machek <pavel@denx.de>
show more ...
|
| fc520894 | 18-Oct-2014 |
Marek Vasut <marex@denx.de> |
arm: socfpga: Move code from misc_init_r() to arch_early_init_r()
Move this initialization code to proper place. The misc_init_r() function is called way too late and the platform initialization cod
arm: socfpga: Move code from misc_init_r() to arch_early_init_r()
Move this initialization code to proper place. The misc_init_r() function is called way too late and the platform initialization code should be executed much earlier.
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Vince Bridgers <vbridger@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Acked-by: Pavel Machek <pavel@denx.de>
show more ...
|
| d0796def | 26-Oct-2014 |
Tom Rini <trini@ti.com> |
Merge http://git.denx.de/u-boot-sunxi |
| 84a6df09 | 26-Oct-2014 |
Tom Rini <trini@ti.com> |
Merge git://git.denx.de/u-boot-dm
Fix a trivial conflict over adding <dm.h>
Conflicts: arch/arm/cpu/armv7/omap3/board.c
Signed-off-by: Tom Rini <trini@ti.com> |
| bf855028 | 08-Oct-2014 |
Jeroen Hofstee <jeroen@myspectrum.nl> |
omap3: board: add missing include and proto
Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl> |
| 52422e37 | 08-Oct-2014 |
Jeroen Hofstee <jeroen@myspectrum.nl> |
leds: missing include
Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl> |
| 5624c6bd | 08-Oct-2014 |
Jeroen Hofstee <jeroen@myspectrum.nl> |
imx: add missing includes
Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl> |
| 19d7bf3d | 08-Oct-2014 |
Jeroen Hofstee <jeroen@myspectrum.nl> |
tegra: make local functions static
Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl> |
| 98431d58 | 08-Oct-2014 |
Jeroen Hofstee <jeroen@myspectrum.nl> |
omap3: make local functions static
Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl> |
| accc9e44 | 22-Oct-2014 |
Hans de Goede <hdegoede@redhat.com> |
sunxi: Add CONFIG_OLD_SUNXI_KERNEL_COMPAT Kconfig option
Add a Kconfig option which users can select when they want to boot older kernels, e.g. the linux-sunxi 3.4 kernels. For now this just forces
sunxi: Add CONFIG_OLD_SUNXI_KERNEL_COMPAT Kconfig option
Add a Kconfig option which users can select when they want to boot older kernels, e.g. the linux-sunxi 3.4 kernels. For now this just forces the pll5 "p" value to 1 (divide by 2) as that is what those kernels are hardcoded too, in the future this may enable further workarounds.
Signed-off-by: Hans de Goede <hdegoede@redhat.com> Reviewed-by: Tom Rini <trini@ti.com> -- Changes in v2: -s/CONFIG_OLD_KERNEL_COMPAT/CONFIG_OLD_SUNXI_KERNEL_COMPAT. -Move the code block setting P(1) for old kernels to where P gets cleared
show more ...
|
| d0dbc286 | 22-Oct-2014 |
Hans de Goede <hdegoede@redhat.com> |
sunxi: dram: Use clock_get_pll5p to calculate mbus, rather then hardcoding
This is a preparation patch for making the pll5 "p" divisor configurable through Kconfig.
Signed-off-by: Hans de Goede <hd
sunxi: dram: Use clock_get_pll5p to calculate mbus, rather then hardcoding
This is a preparation patch for making the pll5 "p" divisor configurable through Kconfig.
Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
show more ...
|
| 9e54f6ee | 22-Oct-2014 |
Hans de Goede <hdegoede@redhat.com> |
sunxi: Add clock_get_pll5p() function
This is a preparation patch for making the pll5 "p" divisor configurable through Kconfig.
Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Camp
sunxi: Add clock_get_pll5p() function
This is a preparation patch for making the pll5 "p" divisor configurable through Kconfig.
Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
show more ...
|
| c757a50b | 22-Oct-2014 |
Chen-Yu Tsai <wens@csie.org> |
ARM: sunxi: Add support for using R_UART as console
The A23 only has UART0 muxed with MMC0. Some of the boards we encountered expose R_UART as a set of pads.
Add support for R_UART so we can have a
ARM: sunxi: Add support for using R_UART as console
The A23 only has UART0 muxed with MMC0. Some of the boards we encountered expose R_UART as a set of pads.
Add support for R_UART so we can have a console while using mmc.
Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Ian Campbell <ijc@hellion.org.uk>
show more ...
|
| 472ed064 | 22-Oct-2014 |
Chen-Yu Tsai <wens@csie.org> |
ARM: sunxi: Allow specifying module in prcm apb0 init function
The prcm apb0 controls multiple modules. Allow specifying which modules to enable clocks and de-assert resets so the function can be re
ARM: sunxi: Allow specifying module in prcm apb0 init function
The prcm apb0 controls multiple modules. Allow specifying which modules to enable clocks and de-assert resets so the function can be reused.
Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Ian Campbell <ijc@hellion.org.uk>
show more ...
|
| 8ebe4f42 | 22-Oct-2014 |
Chen-Yu Tsai <wens@csie.org> |
ARM: sunxi: Add basic A23 support
The basic blocks of the A23 are similar to the A31 (sun6i). Re-use sun6i code for initial clock, gpio, and uart setup.
There is no SPL support for A23, as we do no
ARM: sunxi: Add basic A23 support
The basic blocks of the A23 are similar to the A31 (sun6i). Re-use sun6i code for initial clock, gpio, and uart setup.
There is no SPL support for A23, as we do not have any documentation or sample code for DRAM initialization.
Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Ian Campbell <ijc@hellion.org.uk>
show more ...
|
| ff2b47f6 | 22-Oct-2014 |
Chen-Yu Tsai <wens@csie.org> |
ARM: sunxi: Add support for uart0 on port F (mmc0)
Allwinner SoCs provide uart0 muxed with mmc0, which can then be used with a micro SD breakout board. On the A23, this is the only way to use uart0.
ARM: sunxi: Add support for uart0 on port F (mmc0)
Allwinner SoCs provide uart0 muxed with mmc0, which can then be used with a micro SD breakout board. On the A23, this is the only way to use uart0.
Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Ian Campbell <ijc@hellion.org.uk>
show more ...
|
| 78c396a1 | 04-Oct-2014 |
Chen-Yu Tsai <wens@csie.org> |
ARM: sunxi: Fix reset command on sun6i/sun8i
The watchdog on sun6i/sun8i has a different layout.
Add the new layout and fix up the setup functions so that reset works.
Signed-off-by: Chen-Yu Tsai
ARM: sunxi: Fix reset command on sun6i/sun8i
The watchdog on sun6i/sun8i has a different layout.
Add the new layout and fix up the setup functions so that reset works.
Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Ian Campbell <ijc@hellion.org.uk> [ ijc -- removed sun5i workaround from sun6i/sun8i codepath as discussed ]
show more ...
|
| 8a6564da | 03-Oct-2014 |
Maxime Ripard <maxime.ripard@free-electrons.com> |
ARM: sunxi: Add basic A31 support
Add a new sun6i machine that supports UART and MMC.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Hans de Goede <hdegoede@redhat.c
ARM: sunxi: Add basic A31 support
Add a new sun6i machine that supports UART and MMC.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> [wens@csie.org: use SPDX labels, adapt to Kconfig system, drop ifdef around mmc and smp code, drop MACH_TYPE] Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Ian Campbell <ijc@hellion.org.uk>
show more ...
|
| 77115397 | 03-Oct-2014 |
Maxime Ripard <maxime.ripard@free-electrons.com> |
ARM: sun6i: Setup the A31 UART0 muxing
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> [wens@csie.org: commit message was "ARM: sun
ARM: sun6i: Setup the A31 UART0 muxing
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> [wens@csie.org: commit message was "ARM: sunxi: Setup the A31 UART0 muxing"] [wens@csie.org: reorder #ifs by SUN?I] [wens@csie.org: replace magic numbers with GPIO definitions] Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Ian Campbell <ijc@hellion.org.uk>
show more ...
|
| 14177e47 | 03-Oct-2014 |
Chen-Yu Tsai <wens@csie.org> |
ARM: sun6i: Add clock support
This patch adds the basic clocks support for the Allwinner A31 (sun6i) processor. This code will not been compiled until the build is hooked up in a later patch. It has
ARM: sun6i: Add clock support
This patch adds the basic clocks support for the Allwinner A31 (sun6i) processor. This code will not been compiled until the build is hooked up in a later patch. It has been split out to keep the patches manageable.
This includes changes from the following commits from u-boot-sunxi:
a92051b ARM: sunxi: Add sun6i clock controller structure 1f72c6f ARM: sun6i: Setup the UART0 clocks 5f2e712 ARM: sunxi: Enable pll6 by default on all models 2be2f2a ARM: sunxi-mmc: Add mmc support for sun6i / A31 12e1633 ARM: sun6i: Add initial clock setup for SPL 1a9c9c6 ARM: sunxi: Split clock code into common, sun4i and sun6i code 0b194ee ARM: sun6i: Properly setup the PLL LDO in clock_init_safe b54c626 sunxi: avoid sr32 for APB1 clock setup. 68fe29c sunxi: remove magic numbers from clock_get_pll{5,6} c89867d sunxi: clocks: clock_get_pll5 prototype and coding style 501ab1e ARM: sunxi: Fix sun6i PLL6 settings 37f669b ARM: sunxi: Fix macro names for mmc and uart reset offsets 61de1e6 ARM: sunxi: Correct comment for MBUS1 register in sun6i clock definitions
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Ian Campbell <ijc@hellion.org.uk> Signed-off-by: Hans de Goede <hdegoede@redhat.com> [wens@csie.org: styling fixes reported by checkpatch.pl] [wens@csie.org: drop unsupported SPL code block and unused gpio.h header] Signed-off-by: Chen-Yu Tsai <wens@csie.org> Cc: Tom Cubie <Mr.hipboi@gmail.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
show more ...
|
| 174deb76 | 03-Oct-2014 |
Oliver Schinagl <oliver@schinagl.nl> |
ARM: sun6i: Add support for the power reset control module found on the A31
The A31 has a new module called PRCM, or Power, Reset Control Module. This module controls clocks and resets for RTC block
ARM: sun6i: Add support for the power reset control module found on the A31
The A31 has a new module called PRCM, or Power, Reset Control Module. This module controls clocks and resets for RTC block modules, and also PLL biasing in the main clock module.
This patch adds the register definitions, and also enables the clocks and resets for the RTC block PIO (pin controller) and P2WI (push-pull 2 wire interface) which is used to talk to the PMIC.
Signed-off-by: Oliver Schinagl <oliver@schinagl.nl> Signed-off-by: Hans de Goede <hdegoede@redhat.com> [wens@csie.org: spacing fixes reported by checkpatch.pl] [wens@csie.org: Use setbits helper in PRCM init function] [wens@csie.org: rephrase commit message to explain what the hardware supports and what we actually enable] Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Ian Campbell <ijc@hellion.org.uk>
show more ...
|
| ea520947 | 03-Oct-2014 |
Chen-Yu Tsai <wens@csie.org> |
ARM: sunxi: Use macro values for setting UART GPIO pull-ups
We have already defined macros for pull-up/down values in the GPIO header. Use them instead of magic numbers when configuring the UART pin
ARM: sunxi: Use macro values for setting UART GPIO pull-ups
We have already defined macros for pull-up/down values in the GPIO header. Use them instead of magic numbers when configuring the UART pins.
Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Ian Campbell <ijc@hellion.org.uk>
show more ...
|
| d064cbff | 23-Oct-2014 |
Masahiro Yamada <yamada.m@jp.panasonic.com> |
dm: serial: use Driver Model for UniPhier serial driver
This commit converts UniPhier on-chip serial driver to driver model.
Since UniPhier SoCs do not have Device Tree support, some board files sh
dm: serial: use Driver Model for UniPhier serial driver
This commit converts UniPhier on-chip serial driver to driver model.
Since UniPhier SoCs do not have Device Tree support, some board files should be added under arch/arm/cpu/armv7/uniphier/ph1-*/ directories. (Device Tree support for UniPhier platform is still under way.)
Now the base address and master clock frequency are passed from platform data, so CONFIG_SYS_UNIPHIER_SERIAL_BASE* and CONFIG_SYS_UNIPHIER_UART_CLK should be removed.
Tested on UniPhier PH1-LD4 ref board.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Simon Glass <sjg@chromium.org>
show more ...
|
| b3f4ca11 | 23-Oct-2014 |
Simon Glass <sjg@chromium.org> |
dm: omap3: Move to driver model for GPIO and serial
Adjust the configuration for the am33xx boards, including beagleboard, to use driver model.
Signed-off-by: Simon Glass <sjg@chromium.org> Acked-b
dm: omap3: Move to driver model for GPIO and serial
Adjust the configuration for the am33xx boards, including beagleboard, to use driver model.
Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Tom Rini <trini@ti.com>
show more ...
|
| 4119e06d | 23-Oct-2014 |
Simon Glass <sjg@chromium.org> |
dm: am33xx: Provide platform data for serial
Provide suitable platform data for am33xx boards, so that these boards can use driver model for serial.
Signed-off-by: Simon Glass <sjg@chromium.org> Re
dm: am33xx: Provide platform data for serial
Provide suitable platform data for am33xx boards, so that these boards can use driver model for serial.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@ti.com>
show more ...
|