ARM: DRA7: EMIF: Update SDRAM_REF_CTRL register value

The value in SDRAM_REF_CTRL controls the delay time between
the initial rising edge of DDR_RESETn to rising edge of DDR_CKE
(JEDEC specs this as

ARM: DRA7: EMIF: Update SDRAM_REF_CTRL register value

The value in SDRAM_REF_CTRL controls the delay time between
the initial rising edge of DDR_RESETn to rising edge of DDR_CKE
(JEDEC specs this as 500us). In order to achieve this, SDRAM_REF_CTRL
should be written with a value corresponding to 500us delay before
starting DDR initialization sequence, and configure proper
value at the end of sequence.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>

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ARM: DRA72x: DDR3: Fix EMIF timings for 666MHz clock

DDR3 timing and latency paramenters were not configured
correctly for 666MHz. Fixing the timing and latency values
according to Data sheet.
This

ARM: DRA72x: DDR3: Fix EMIF timings for 666MHz clock

DDR3 timing and latency paramenters were not configured
correctly for 666MHz. Fixing the timing and latency values
according to Data sheet.
This fixes the random crashes seen on DRA72-evm.

Signed-off-by: Angela Stegmaier <angelabaker@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>

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Merge git://git.denx.de/u-boot-samsung

Merge git://git.denx.de/u-boot-dm

Merge branch 'rmobile' of git://git.denx.de/u-boot-sh

Exynos: Clock: Cleanup soc_get_periph_rate

Since we have src, div and pre-div mask bits defined corresponding
to peripherals, calculation of clock specific to I2C appears
redundant and confusing. Us

Exynos: Clock: Cleanup soc_get_periph_rate

Since we have src, div and pre-div mask bits defined corresponding
to peripherals, calculation of clock specific to I2C appears
redundant and confusing. Using clk_bit_info struct we can write
calculations generic to all peripherals which makes code easy to
understand and free from peripheral specific exceptions.

Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>

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Exynos: clock: change mask bits as per peripheral

We have assumed and kept mask bits for divider and pre-divider
as 0xf and 0xff, respectively. But these mask bits change from
one peripheral to anot

Exynos: clock: change mask bits as per peripheral

We have assumed and kept mask bits for divider and pre-divider
as 0xf and 0xff, respectively. But these mask bits change from
one peripheral to another, and hence, need to be specified in
accordance with the peripherals.

Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>

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Exynos5: Use clock_get_periph_rate generic API

Replacing SoC and peripheral specific function calls with generic
clock_get_periph_rate calls to get the peripheral clocks.
Also, removing dead code of

Exynos5: Use clock_get_periph_rate generic API

Replacing SoC and peripheral specific function calls with generic
clock_get_periph_rate calls to get the peripheral clocks.
Also, removing dead code of peripheral and SoC specific function
implementations which was used earlier for fetching peripheral clocks.
This code is not being used anymore because of the introduction
of generic clock_get_periph_rate function.

Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>

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Exynos5: Fix exynos5_get_periph_rate calculations

exynos5_get_periph_rate function reads incorrect div for
SDMMC2 & 3. It also reads prediv and does division only for
SDMMC0 & 2 when actually variou

Exynos5: Fix exynos5_get_periph_rate calculations

exynos5_get_periph_rate function reads incorrect div for
SDMMC2 & 3. It also reads prediv and does division only for
SDMMC0 & 2 when actually various other peripherals need that.
Adding changes to fix these mistakes in periph rate calculation.

Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>

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Exynos542x: Add and enable get_periph_rate support

We planned to fetch peripheral rate through one generic API per
peripheral. These generic peripheral functions are in turn
expected to fetch apt va

Exynos542x: Add and enable get_periph_rate support

We planned to fetch peripheral rate through one generic API per
peripheral. These generic peripheral functions are in turn
expected to fetch apt values from a function refactored as
per SoC versions. This patch adds support for fetching peripheral
rates for Exynos5420 and Exynos5800.

Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>

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Exynos542x: Move exynos5420_get_pll_clk up and rename

Moving exynos5420_get_pll_clk function definition up in the
code to keep it together with rest of SoC_get_pll_clk functions.
This makes code mor

Exynos542x: Move exynos5420_get_pll_clk up and rename

Moving exynos5420_get_pll_clk function definition up in the
code to keep it together with rest of SoC_get_pll_clk functions.
This makes code more legible and also removes the need of
declaration when called before the position of definition in
code. Also, renaming exynos5420_get_pll_clk to
exynos542x_get_pll_clk because it is being used for both Exynos
5420 and 5800.

Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>

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Exynos5: Fix compiler warnings due to clock_get_periph_rate

Apparently, members of clk_bit_info array do not map correctly
to the members of enum periph_id. This mapping got broken after
we changed

Exynos5: Fix compiler warnings due to clock_get_periph_rate

Apparently, members of clk_bit_info array do not map correctly
to the members of enum periph_id. This mapping got broken after
we changed periph_id(s) to reflect interrupt number instead of
their position in a sequence. This patch intends to fix above
mentioned issue.

Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>

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EXYNOS5: Add function to enable exynos5420 usbdev phy ctrl

Exynos5420 has different registers with other exynos5 SoCs to control
usb device phy, so need separated function to enable exynos5420 usb
d

EXYNOS5: Add function to enable exynos5420 usbdev phy ctrl

Exynos5420 has different registers with other exynos5 SoCs to control
usb device phy, so need separated function to enable exynos5420 usb
device phy.

Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>

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arm: exynos: fix the div value for set_mmc_clk

The most exynos used the "Ratio + 1" as div value.
And value at register is "Ratio".
So if want to set exact value, it needs to subtract one.

Value a

arm: exynos: fix the div value for set_mmc_clk

The most exynos used the "Ratio + 1" as div value.
And value at register is "Ratio".
So if want to set exact value, it needs to subtract one.

Value at register ("Ratio") = div - 1

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>

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arm: rmobile: r8a7794: Enable SMP mode of Auxiliary Control Register

r8a7794 uses ARM SoC of CA7 base. If we want to use dcache on CA7, we
need to enable SMP bit of Auxiliary Control Register.

Sign

arm: rmobile: r8a7794: Enable SMP mode of Auxiliary Control Register

r8a7794 uses ARM SoC of CA7 base. If we want to use dcache on CA7, we
need to enable SMP bit of Auxiliary Control Register.

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>

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arm: rmobile: Add SILK board support

SILK is an entry level development board based on R-Car E2 SoC (R8A7794)

This commit supports the following peripherals:
- SCIF, I2C, Ethernet, QSPI, MMC, USB H

arm: rmobile: Add SILK board support

SILK is an entry level development board based on R-Car E2 SoC (R8A7794)

This commit supports the following peripherals:
- SCIF, I2C, Ethernet, QSPI, MMC, USB Host

Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Reviewed-by: Tom Rini <trini@ti.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>

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dm: Kconfig: Move CONFIG_SYS_MALLOC_F_LEN to Kconfig

Move this option to Kconfig and update all boards.
Signed-off-by: Simon Glass <sjg@chromium.org>

dm: omap3: Move driver model CONFIGs to Kconfig

Remove driver model CONFIGs from the board config headers and use Kconfig
instead.

Signed-off-by: Simon Glass <sjg@chromium.org>

dm: tegra: Move driver model CONFIGs to Kconfig

Remove driver model CONFIGs from the board config headers and use Kconfig
instead.

Signed-off-by: Simon Glass <sjg@chromium.org>

dm: exynos: Move driver model CONFIGs to Kconfig

Remove driver model CONFIGs from the board config headers and use Kconfig
instead.

Signed-off-by: Simon Glass <sjg@chromium.org>

dm: Move Raspberry Pi driver model CONFIGs to Kconfig

Remove driver model CONFIGs from the board config header and use Kconfig
instead.

Signed-off-by: Simon Glass <sjg@chromium.org>

Merge branch 'master' of git://git.denx.de/u-boot-atmel

Merge branch 'master' of git://www.denx.de/git/u-boot-imx

arm: mxs: Add 'Wait for JTAG user' if booted in JTAG mode

When booting in JTAG mode, there is no way to use soft break-points, and
no way of knowing when SPL has finished executing (so the user can

arm: mxs: Add 'Wait for JTAG user' if booted in JTAG mode

When booting in JTAG mode, there is no way to use soft break-points, and
no way of knowing when SPL has finished executing (so the user can issue
a 'halt' command to load u-boot.bin for example)

Add a debug output and simple loop to stop execution at the completion of
the SPL initialisation as a pseudo break-point when booting in JTAG mode

Signed-off-by: Graeme Russ <gruss@tss-engineering.com>

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arm: mxs: Enable booting of mx28 without battery

Section 4.1.2 of Freescale Application Note AN4199 describes the
configuration required to operate the mx28 from a 5V source without a
battery.

This

arm: mxs: Enable booting of mx28 without battery

Section 4.1.2 of Freescale Application Note AN4199 describes the
configuration required to operate the mx28 from a 5V source without a
battery.

This patch changes the behaviour of the dropout control of the DC-DC
converter (refer to section 11.12.9 of the mx28 Application Processor
Reference Manual - Document Number: MCIMX28RM, Rev 2, 08/2013) to the
following:
- Always use 4P2 Linear Regulator if CONFIG_SYS_MXS_VDD5V_ONLY is defined
- Switch between 4P2 Linear Regulator and Battery, using whichever has
the highest voltage if CONFIG_SYS_MXS_VDD5V_ONLY isnot set (this is
the same as the pre-patch behaviour)

Signed-off-by: Graeme Russ <gruss@tss-engineering.com>
Signed-off-by: Damien Gotfroi <dgotfroi@greenwatch.be>

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