History log of /rk3399_rockchip-uboot/arch/arm/cpu/armv7/ls102xa/soc.c (Results 1 – 14 of 14)
Revision Date Author Comments
# 3fea9536 15-Apr-2017 Tom Rini <trini@konsulko.com>

Merge branch 'master' of git://git.denx.de/u-boot-video


# b215fb3f 11-Apr-2017 Sanchayan Maity <maitysanchayan@gmail.com>

Convert CONFIG_FSL_DCU_FB to Kconfig

Rename CONFIG_FSL_DCU_FB to CONFIG_VIDEO_FSL_DCU_FB
and convert it to Kconfig.

Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
Reviewed-by: Stefan Agn

Convert CONFIG_FSL_DCU_FB to Kconfig

Rename CONFIG_FSL_DCU_FB to CONFIG_VIDEO_FSL_DCU_FB
and convert it to Kconfig.

Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
Reviewed-by: Stefan Agner <stefan.agner@toradex.com>
Reviewed-by: Alison Wang <alison.wang@nxp.com>

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# 711b5341 12-Oct-2016 Tom Rini <trini@konsulko.com>

Merge git://git.denx.de/u-boot-fsl-qoriq

Signed-off-by: Tom Rini <trini@konsulko.com>

Conflicts:
include/configs/ls1021aqds.h
include/configs/ls1021atwr.h


# f85a8e8d 14-Sep-2016 Xiaoliang Yang <xiaoliang.yang@nxp.com>

armv7: LS1021a: enable i-cache in start.S

Delete CONFIG_SKIP_LOWLEVEL_INIT define in ls1021atwr.h and
ls1021aqds.h can let it run cpu_init_cp15 to enable i-cache. First
stage of u-boot can run faste

armv7: LS1021a: enable i-cache in start.S

Delete CONFIG_SKIP_LOWLEVEL_INIT define in ls1021atwr.h and
ls1021aqds.h can let it run cpu_init_cp15 to enable i-cache. First
stage of u-boot can run faster after that. There is a description
about skip lowlevel init in board/freescale/ls1021atwr/README.

Signed-off-by: Xiaoliang Yang <xiaoliang.yang@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

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# cbe7706a 26-Sep-2016 Tom Rini <trini@konsulko.com>

Merge git://git.denx.de/u-boot-fsl-qoriq

trini: Drop local memset() from
examples/standalone/mem_to_mem_idma2intr.c

Signed-off-by: Tom Rini <trini@konsulko.com>


# b392a6d4 02-Aug-2016 Hou Zhiqiang <Zhiqiang.Hou@nxp.com>

fsl-layerscape: Add workaround for PCIe erratum A010315

As the access to serders protocol unselected PCIe controller will
hang. So disable the R/W permission to unselected PCIe controller
including

fsl-layerscape: Add workaround for PCIe erratum A010315

As the access to serders protocol unselected PCIe controller will
hang. So disable the R/W permission to unselected PCIe controller
including its CCSR, IO space and memory space according to the
serders protocol field of RCW.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

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# 341238fd 02-Aug-2016 Hou Zhiqiang <Zhiqiang.Hou@nxp.com>

arm: fsl-layerscape: move forward the non-secure access permission setup

Move forward the basic non-secure access enable operation, so the
subsequent individual device access permission can override

arm: fsl-layerscape: move forward the non-secure access permission setup

Move forward the basic non-secure access enable operation, so the
subsequent individual device access permission can override it.
And collect the dispersed callers in board level, and then move
them to SoC level.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

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# e1417c7b 24-Feb-2016 Tom Rini <trini@konsulko.com>

Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq


# a08b1921 05-Feb-2016 Alison Wang <b18965@freescale.com>

armv7: ls102xa: Move smmu and stream id initialization into the common soc code

The initialization for smmu and stream id is moved into the common soc
code.

Signed-off-by: Alison Wang <alison.wang@

armv7: ls102xa: Move smmu and stream id initialization into the common soc code

The initialization for smmu and stream id is moved into the common soc
code.

Signed-off-by: Alison Wang <alison.wang@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

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# e6e3faa5 15-Dec-2015 Tom Rini <trini@konsulko.com>

Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq


# 6c4a1eba 05-Dec-2015 Yao Yuan <yao.yuan@freescale.com>

armv7/fsl-ls102xa: Workaround for DDR erratum A008514

This is a workaround for hardware erratum.
Write the value of 63b2_0042h to EDDRTQCFG will optimal the
memory controller performance.

The value

armv7/fsl-ls102xa: Workaround for DDR erratum A008514

This is a workaround for hardware erratum.
Write the value of 63b2_0042h to EDDRTQCFG will optimal the
memory controller performance.

The value: 63b2_0042h comes from the hardware team.

Signed-off-by: Yuan Yao <yao.yuan@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

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# 0b8bc631 05-Dec-2015 Yao Yuan <yao.yuan@freescale.com>

armv7: ls102xa: cci-400: Enable snoop and DVM message requests.

Enable snoop and DVM message on all CCI-400 slave ports. Setting
on disabled feature (snoop or DVM) is ignored by CCI-400.

Signed-off

armv7: ls102xa: cci-400: Enable snoop and DVM message requests.

Enable snoop and DVM message on all CCI-400 slave ports. Setting
on disabled feature (snoop or DVM) is ignored by CCI-400.

Signed-off-by: Yuan Yao <yao.yuan@freescale.com>
[York Sun: Add commit message]
Reviewed-by: York Sun <yorksun@freescale.com>

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# 762b3535 05-Dec-2015 Yao Yuan <yao.yuan@freescale.com>

arm: ls102xa: enable all the snoop signal for masters.

Enable the IP feature's snoop signal to support
hardware snoop for cache coherence.

SNPCNFGCR contains the bits to drive snoop signal
for vari

arm: ls102xa: enable all the snoop signal for masters.

Enable the IP feature's snoop signal to support
hardware snoop for cache coherence.

SNPCNFGCR contains the bits to drive snoop signal
for various masters.

Signed-off-by: Yuan Yao <yao.yuan@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

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# 7ba02618 05-Dec-2015 Yao Yuan <yao.yuan@freescale.com>

arm: ls1021a: merge SoC specific code in a separate file

Create a soc.c file to put the code for soc special settings.

Signed-off-by: Yuan Yao <yao.yuan@freescale.com>
Reviewed-by: York Sun <yorksu

arm: ls1021a: merge SoC specific code in a separate file

Create a soc.c file to put the code for soc special settings.

Signed-off-by: Yuan Yao <yao.yuan@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

show more ...