| #
f1683aa7 |
| 06-Apr-2017 |
Simon Glass <sjg@chromium.org> |
board_f: Rename initdram() to dram_init()
This allows us to use the same DRAM init function on all archs. Add a dummy function for arc, which does not use DRAM init here.
Signed-off-by: Simon Glass
board_f: Rename initdram() to dram_init()
This allows us to use the same DRAM init function on all archs. Add a dummy function for arc, which does not use DRAM init here.
Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Dummy function on nios2] Signed-off-by: Tom Rini <trini@konsulko.com>
show more ...
|
| #
5fee9489 |
| 11-Apr-2016 |
Tom Rini <trini@konsulko.com> |
Merge branch 'master' of git://git.denx.de/u-boot-arc
|
| #
8b15010b |
| 20-Feb-2016 |
Alexey Brodkin <abrodkin@synopsys.com> |
arc: get rid of running_on_hw
ISS is obsolete now and nSIM is used for simulation instead. In its turn nSIM properly handles baud-rate settings so get rid of now useless check.
Signed-off-by: Alexe
arc: get rid of running_on_hw
ISS is obsolete now and nSIM is used for simulation instead. In its turn nSIM properly handles baud-rate settings so get rid of now useless check.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
show more ...
|
| #
1254ff97 |
| 10-Jul-2015 |
Stefano Babic <sbabic@denx.de> |
Merge branch 'master' of git://git.denx.de/u-boot
|
| #
ef639e6f |
| 18-May-2015 |
Alexey Brodkin <Alexey.Brodkin@synopsys.com> |
arc: significant cache rework
[1] Align cache management functions to those in Linux kernel. I.e.: a) Use the same functions for all cache ops (D$ Inv/Flush) b) Split cache ops in 3 sub-func
arc: significant cache rework
[1] Align cache management functions to those in Linux kernel. I.e.: a) Use the same functions for all cache ops (D$ Inv/Flush) b) Split cache ops in 3 sub-functions: "before", "lineloop" and "after". That way we may re-use "before" and "after" functions for region and full cache ops.
[2] Implement full-functional L2 (SLC) management. Before SLC was simply disabled early on boot. It's also possible to enable or disable L2 cache from config utility.
[3] Disable/enable corresponding caches early on boot. So if U-Boot is configured to use caches they will be used at all times (this is useful in partucular for speed-up of relocation).
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
show more ...
|
| #
b491d975 |
| 10-Apr-2015 |
Albert ARIBAUD <albert.u.boot@aribaud.net> |
Merge branch 'u-boot/master'
|
| #
d68df028 |
| 03-Apr-2015 |
Tom Rini <trini@konsulko.com> |
Merge git://git.denx.de/u-boot-arc
|
| #
3fb80163 |
| 24-Feb-2015 |
Alexey Brodkin <abrodkin@synopsys.com> |
arc: clean-up init procedure
Intention behind this work was elimination of as much assembly-written code as it is possible.
In case of ARC we already have relocation fix-up implemented in C so why
arc: clean-up init procedure
Intention behind this work was elimination of as much assembly-written code as it is possible.
In case of ARC we already have relocation fix-up implemented in C so why don't we use C for U-Boot copying, .bss zeroing etc.
It turned out x86 uses pretty similar approach so we re-used parts of code in "board_f.c" initially implemented for x86.
Now assembly usage during init is limited to stack- and frame-pointer setup before and after relocation.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Cc: Simon Glass <sjg@chromium.org>
show more ...
|
| #
e72d3443 |
| 13-Feb-2015 |
Stefano Babic <sbabic@denx.de> |
Merge branch 'master' of git://git.denx.de/u-boot
|
| #
768f6096 |
| 20-Jan-2015 |
Tom Rini <trini@ti.com> |
Merge git://git.denx.de/u-boot-arc
|
| #
660d5f0d |
| 27-Dec-2014 |
Alexey Brodkin <abrodkin@synopsys.com> |
arc: move common sources in library
"reset.c" and "cpu.c" have no architecture-specific code at all. Others are applicable to either ARC CPU.
This change is a preparation to submission of ARCv2 arc
arc: move common sources in library
"reset.c" and "cpu.c" have no architecture-specific code at all. Others are applicable to either ARC CPU.
This change is a preparation to submission of ARCv2 architecture port.
Even though ARCv1 and ARCv2 ISAs are not binary compatible most of built-in modules still have the same programming model - AUX registers are mapped in the same addresses and hold the same data (new featues extend existing ones).
So only low-level assembly code (start-up, interrupt handlers) is left as CPU(actually ISA)-specific. This significantyl simplifies maintenance of multiple CPUs/ISAs.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Signed-off-by: Igor Guryanov <guryanov@synopsys.com>
show more ...
|