arc: Update exception & interrupt handling for ARCv2Initially IVT for ARCv2 was simply copypasted from ARCompactwith some selected fixes so basic stuff works.Now we update it with more ARCv2 spe
arc: Update exception & interrupt handling for ARCv2Initially IVT for ARCv2 was simply copypasted from ARCompactwith some selected fixes so basic stuff works.Now we update it with more ARCv2 specific vectors like * Software Interrupt * Division by zero * Data cache consistency error * Misaligned accessAlso normal interrupts are now implemented properly and extened toall possible 240 items.Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
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arc: merge common start-up code between ARC and ARCv2Even though ARCompact and ARCv2 are not binary compatible most ofassembly instructions are used in both. With this change we'll get ridof dupl
arc: merge common start-up code between ARC and ARCv2Even though ARCompact and ARCv2 are not binary compatible most ofassembly instructions are used in both. With this change we'll get ridof duplicate code.Still IVTs are implemented differently so we're keeping them in separatefiles.Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
arc: introduce U-Boot port for ARCv2 ISAARC HS and ARC EM are new cores based on ARCv2 ISA which is binaryincompatible with ISAv1 (AKA ARCompact).Significant difference between ISAv2 and v1 is i
arc: introduce U-Boot port for ARCv2 ISAARC HS and ARC EM are new cores based on ARCv2 ISA which is binaryincompatible with ISAv1 (AKA ARCompact).Significant difference between ISAv2 and v1 is implementation ofinterrupt vector table.In v1 it is implemented in the same way as on many other architectures -as a special location where user may put whether code executed in place(if machine word of space is enough) or jump to a full-scale interrupthandler.In v2 interrupt table is just an array of adresses of real interrupthandlers. That requires a separate section for IVT that is not encodedas code by assembler.This change adds support for following cores: * ARC EM6 (simple 32-bit microcontroller without MMU) * ARC HS36 (advanced 32-bit microcontroller without MMU) * ARC HS38 (advanced 32-bit microcontroller with MMU)As a part of ARC HS38 new version of MMU (v4) was introduced.Also this change adds AXS131 board which is the same DW ARC SDP base board butwith ARC HS38 CPU tile.Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>