libc/snprintf: add support to print "%" character

Enable snprintf()/vsnprintf() in TF-A to print "%" character as C
standard, which may be used in platform porting to print percentage
information.

libc/snprintf: add support to print "%" character

Enable snprintf()/vsnprintf() in TF-A to print "%" character as C
standard, which may be used in platform porting to print percentage
information.

Signed-off-by: Heyi Guo <guoheyi@linux.alibaba.com>
Change-Id: I9b296372a1002046eabac1df5e8eb99a27efd4a8

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libc/printf: add support to print "%" character

Enable printf() in TF-A to print "%" character as C standard, which
may be used in platform porting to print percentage information.

Signed-off-by: H

libc/printf: add support to print "%" character

Enable printf() in TF-A to print "%" character as C standard, which
may be used in platform porting to print percentage information.

Signed-off-by: Heyi Guo <guoheyi@linux.alibaba.com>
Change-Id: I7af2f1d153548e426f423fce15dc48b0da56c622

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drivers: move scmi-msg out of st

Make the scmi-msg driver reused by others.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Change-Id: I5bc35fd4dab70f45c09b8aab65af4209cf23b124

qemu/qemu_sbsa: add support for sbsa-ref Embedded Controller

This allows PSCI in TF-A to signal platform power states to QEMU
via a controller in secure space.

This required a sbsa-ref specific ver

qemu/qemu_sbsa: add support for sbsa-ref Embedded Controller

This allows PSCI in TF-A to signal platform power states to QEMU
via a controller in secure space.

This required a sbsa-ref specific version of PSCI functions for the
platform. Also adjusted the MMU range to also include the new EC.

Add a new MMU region for the embedded controller and increase the
size of xlat tables by one for the new region.

Signed-off-by: Graeme Gregory <graeme@nuviainc.com>
Change-Id: Iece8a88947f11e82ab8988e460a8a66ad175a5ee

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qemu/qemu_sbsa: topology is different from qemu so add handling

sbsa-ref in QEMU creates clusers of 8 cores, it may create up to 512
cores in upto 64 clusters. Implement a qemu_sbsa specific topolog

qemu/qemu_sbsa: topology is different from qemu so add handling

sbsa-ref in QEMU creates clusers of 8 cores, it may create up to 512
cores in upto 64 clusters. Implement a qemu_sbsa specific topology file
and increase the BL31_SIZE to accommodate the bigger table sizes. Change
platform_def.h for new topology. Correct PLATFORM_CPU_PER_CLUSTER_SHIFT so
plat_helpers.S calculates correct result.

Signed-off-by: Graeme Gregory <graeme@nuviainc.com>
Change-Id: Idc5d70394c0956b759ad2c86f9fda8f293f2cfa7

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qemu/common : change DEVICE2 definition for MMU

DEVICE2 is not currently used on qemu platform but is needed for
a future patch for qemu_sbsa platform. Change its definition to
RW and add it to all

qemu/common : change DEVICE2 definition for MMU

DEVICE2 is not currently used on qemu platform but is needed for
a future patch for qemu_sbsa platform. Change its definition to
RW and add it to all levels of arm-tf similar to DEVICE1 definition.

Signed-off-by: Graeme Gregory <graeme@nuviainc.com>
Change-Id: I03495471bfd423b61ad44ec4953fb25f76aa54bf

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qemu/aarch64/plat_helpers.S : calculate the position shift

Rather than re-create this file in multiple qemu variants instead
caclulate the shift needed to convert MPIDR to position.

Add a new PLATF

qemu/aarch64/plat_helpers.S : calculate the position shift

Rather than re-create this file in multiple qemu variants instead
caclulate the shift needed to convert MPIDR to position.

Add a new PLATFORM_CPU_PER_CLUSTER_SHIFT define in platform_def.h
for both qemu and qemu_sbsa to enable this calculation.

Signed-off-by: Graeme Gregory <graeme@nuviainc.com>
Change-Id: I0e3a86354aa716d95150a3a34b15287cd70c8fd2

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Merge "fdts: stm32mp1: add support for Linux Automation MC-1 board" into integration

plat/qemu: Use RNDR in stack protector

When getting a stack protector canary value, check
if cpu supports FEAT_RNG and use that. Fallback to
old method of using a (hardcoded value ^ timer).

Signed-

plat/qemu: Use RNDR in stack protector

When getting a stack protector canary value, check
if cpu supports FEAT_RNG and use that. Fallback to
old method of using a (hardcoded value ^ timer).

Signed-off-by: Tomas Pilar <tomas@nuviainc.com>
Change-Id: I8181acf8e31661d4cc82bc3a4078f8751909e725

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fdts: stm32mp1: add support for Linux Automation MC-1 board

The Linux Automation MC-1 is a SBC built around the Octavo Systems
OSD32MP15x SiP. The SiP features up to 1 GB DDR3 RAM, EEPROM and
PMIC.

fdts: stm32mp1: add support for Linux Automation MC-1 board

The Linux Automation MC-1 is a SBC built around the Octavo Systems
OSD32MP15x SiP. The SiP features up to 1 GB DDR3 RAM, EEPROM and
PMIC. The board has eMMC and a SD slot for storage.

The SDRAM calibration values are taken as is from the DKx boards, which
seem to be suitable for operation at German room temperature.

This is deemed ok for now, but for use in the field, the SiP will likely
need to have its timings determined in a climate chamber.

Change-Id: I5f43a61930151ae9d1df2ea7d0f6f9697c813ce0
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>

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marvell: uart: a3720: Fix macro name for 6th bit of Status Register

This patch does not change code, it only updates comments and macro name
for 6th bit of Status Register. So TF-A binary stay same.

marvell: uart: a3720: Fix macro name for 6th bit of Status Register

This patch does not change code, it only updates comments and macro name
for 6th bit of Status Register. So TF-A binary stay same.

6th bit of the Status Register is named TX EMPTY and is set to 1 when both
Transmitter Holding Register (THR) or Transmitter Shift Register (TSR) are
empty. It is when all characters were already transmitted.

There is also TX FIFO EMPTY bit in the Status Register which is set to 1
only when THR is empty.

In both console_a3700_core_init() and console_a3700_core_flush() functions
we should wait until both THR and TSR are empty therefore we should check
6th bit of the Status Register.

So current code is correct, just had misleading macro names and comments.
This change fixes this "documentation" issue, fixes macro name for 6th bit
of the Status Register and also updates comments.

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I19e4e7f53a90bcfb318e6dd1b1249b6cbf81c4d3

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marvell: uart: a3720: Implement console_a3700_core_getc

Implementation is simple, just check if there is a pending character in
RX FIFO via RXRDY bit of Status Register and if yes, read it from
UART

marvell: uart: a3720: Implement console_a3700_core_getc

Implementation is simple, just check if there is a pending character in
RX FIFO via RXRDY bit of Status Register and if yes, read it from
UART_RX_REG register.

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I226b6e336f44f5d0ca8dcb68e49a68e8f2f49708

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Merge changes I3c0a402f,I9ce5b9df,I08719015,If541278f,I99f1a697 into integration

* changes:
doc: renesas: Update code owner for Renesas platforms
doc: renesas: Document platforms based on RZ/G2

Merge changes I3c0a402f,I9ce5b9df,I08719015,If541278f,I99f1a697 into integration

* changes:
doc: renesas: Update code owner for Renesas platforms
doc: renesas: Document platforms based on RZ/G2 SoC's
renesas: rzg: Add PFC support for RZ/G2M
renesas: rzg: Add QoS support for RZ/G2M
renesas: rzg: Add support for DRAM initialization

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Makefile: Add FEAT_RNG support define

Define ENABLE_FEAT_RNG that describes whether the
armv8.5 FEAT_RNG is supported in this build. This
allows conditional inclusion of code targetting
RNDR and RND

Makefile: Add FEAT_RNG support define

Define ENABLE_FEAT_RNG that describes whether the
armv8.5 FEAT_RNG is supported in this build. This
allows conditional inclusion of code targetting
RNDR and RNDRRS registers.

Signed-off-by: Tomas Pilar <tomas@nuviainc.com>
Change-Id: Idd632f8b9bc20ea3d8793f55ead88fa12cb08821

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Define registers for FEAT_RNG support

Add ISAR0 feature register read helper, location
of FEAT_RNG bits, feature support helper and the
rndr/rndrrs register read helpers.

Signed-off-by: Tomas Pilar

Define registers for FEAT_RNG support

Add ISAR0 feature register read helper, location
of FEAT_RNG bits, feature support helper and the
rndr/rndrrs register read helpers.

Signed-off-by: Tomas Pilar <tomas@nuviainc.com>
Change-Id: I2a785a36f62a917548e55892ce92fa8b72fcb99d

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Merge changes from topic "certtool-memleak" into integration

* changes:
Use preallocated parts of the HASH struct
Free arguments copied with strdup
Free keys after use
Free X509_EXTENSIONs

Merge "tools: don't clean when building" into integration

Merge changes I36e4d672,I47610cee into integration

* changes:
Workaround for Cortex N1 erratum 1946160
Workaround for Cortex A78 erratum 1951500

Merge changes Ie8922309,I1001bea1,I66265e5e,I2cc0ceda,I04805d72, ... into integration

* changes:
plat: renesas: common: Include ulcb_cpld.h conditionally
plat: renesas: Move to common
plat: re

Merge changes Ie8922309,I1001bea1,I66265e5e,I2cc0ceda,I04805d72, ... into integration

* changes:
plat: renesas: common: Include ulcb_cpld.h conditionally
plat: renesas: Move to common
plat: renesas: aarch64: Move to common
drivers: renesas: Move ddr/qos/qos header files
drivers: renesas: rpc: Move to common
drivers: renesas: avs: Move to common
drivers: renesas: auth: Move to common
drivers: renesas: dma: Move to common
drivers: renesas: watchdog: Move to common
drivers: renesas: rom: Move to common
drivers: renesas: delay: Move to common
drivers: renesas: console: Move to common
drivers: renesas: pwrc: Move to common
drivers: renesas: io: Move to common
drivers: renesas: eMMC: Move to common

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Merge changes Id2b1822c,Ia9a563a1,I11f65d49,If9318a51,I46801b56, ... into integration

* changes:
drivers: renesas: Move plat common sources
plat: renesas: Move headers and assembly files to comm

Merge changes Id2b1822c,Ia9a563a1,I11f65d49,If9318a51,I46801b56, ... into integration

* changes:
drivers: renesas: Move plat common sources
plat: renesas: Move headers and assembly files to common folder
plat: renesas: rcar: include: Code cleanup
plat: renesas:rcar: Fix checkpatch warnings
plat: renesas: rcar: Fix checkpatch warnings
plat: renesas:rcar: Code cleanup
plat: renesas: rcar: Fix coding style

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Merge "docs: update fvp version to be used for rdv1 platform" into integration

docs: marvell: armada: Update MARVELL_PLATFORM list and build instructions

The supported MARVELL_PLATFORM list is updated to include the recently added
a80x0_puzzle platform (IEI Puzzle-M801).

Addi

docs: marvell: armada: Update MARVELL_PLATFORM list and build instructions

The supported MARVELL_PLATFORM list is updated to include the recently added
a80x0_puzzle platform (IEI Puzzle-M801).

Additionally building instructions are added for the GST ESPRESSObin-Ultra
board (1 GB, DDR4 RAM variant), which has been tested successfully and booted
TF-A on the board.

Signed-off-by: Luka Kovacic <luka.kovacic@sartura.hr>
Change-Id: Ie5724df27c1ee2e8f6a52664520579e872471e93

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lib/extensions/ras: fix bug of binary search

In ras_interrupt_handler(), binary search end was set to the size of
the ras_interrupt_mappings array, which would cause out of bound
access when the inp

lib/extensions/ras: fix bug of binary search

In ras_interrupt_handler(), binary search end was set to the size of
the ras_interrupt_mappings array, which would cause out of bound
access when the input intr_raw is larger than all the elements in
ras_interrupt_mappings.

Signed-off-by: Heyi Guo <guoheyi@linux.alibaba.com>
Change-Id: Id2cff73177134b09d4d8beb596c3429b98ec5066

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Workaround for Cortex N1 erratum 1946160

Cortex N1 erratum 1946160 is a Cat B erratum present in r0p0, r1p0,
r2p0, r3p0, r3p1, r4p0, and r4p1. The workaround is to insert a DMB ST
before acquire at

Workaround for Cortex N1 erratum 1946160

Cortex N1 erratum 1946160 is a Cat B erratum present in r0p0, r1p0,
r2p0, r3p0, r3p1, r4p0, and r4p1. The workaround is to insert a DMB ST
before acquire atomic instructions without release semantics. This
issue is present starting from r0p0 but this workaround applies to
revisions r3p0, r3p1, r4p0, and r4p1, for previous revisions there is no
workaround.

SDEN can be found here:
https://documentation-service.arm.com/static/5fa9304cd8dacc30eded464f

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I36e4d6728c275f1c2477dcee9b351077cf7c53e4

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Workaround for Cortex A78 erratum 1951500

Cortex A78 erratum 1951500 is a Cat B erratum that applies to revisions
r0p0, r1p0, and r1p1. The workaround is to insert a DMB ST before
acquire atomic in

Workaround for Cortex A78 erratum 1951500

Cortex A78 erratum 1951500 is a Cat B erratum that applies to revisions
r0p0, r1p0, and r1p1. The workaround is to insert a DMB ST before
acquire atomic instructions without release semantics. This workaround
works on revisions r1p0 and r1p1, in r0p0 there is no workaround.

SDEN can be found here:
https://documentation-service.arm.com/static/5fb66157ca04df4095c1cc2e

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I47610cee75af6a127ea65edc4d5cffc7e6a2d0a3

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