Merge "fix(intel): support DDR In-line and Out-of-Band ECC handling" into integration

Merge "feat(intel): move common functions to common lib files" into integration

Merge "fix(intel): add 5us delay before Linux reconfig to avoid HNOC hang" into integration

Merge changes from topic "xlnx_fix_gen_unused_var" into integration

* changes:
fix(console): create unique variable name
fix(bl31): declare function as static
fix(psci): initialise variable to

Merge changes from topic "xlnx_fix_gen_unused_var" into integration

* changes:
fix(console): create unique variable name
fix(bl31): declare function as static
fix(psci): initialise variable to default zero
fix(services): declare unused parameters as void
fix(lib): declare unused parameters as void
fix(platforms): declare unused parameters as void

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Merge "feat(mt8189): add UFS functions used by libbl31.a" into integration

Merge changes Id3360744,Iacb23acd,I2b60cc18,I625e9498,I477143c2, ... into integration

* changes:
feat(mt8189): add EC pin control in SPM
feat(mt8189): add LPM v2 support
feat(mt8189): add SPM

Merge changes Id3360744,Iacb23acd,I2b60cc18,I625e9498,I477143c2, ... into integration

* changes:
feat(mt8189): add EC pin control in SPM
feat(mt8189): add LPM v2 support
feat(mt8189): add SPM common driver support
feat(mt8189): add VCORE DVFS drivers
feat(mt8189): add SPM basic features support
feat(mt8189): add SPM features support
feat(mt8189): enable PMIC low power setting
feat(mt8196): extract common SPM code for reuse

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fix(spmd): skip spurious id while group0 interrupt handling

A spurious ID might be reported by interrupt controller when EL3 starts
handling a Group0 interrupt. This could happen if the interrupt go

fix(spmd): skip spurious id while group0 interrupt handling

A spurious ID might be reported by interrupt controller when EL3 starts
handling a Group0 interrupt. This could happen if the interrupt got
deasserted while the EL3 software triages it.

Change-Id: I3b0e0d9203fec4c0c76b9704eee53f2208ae64c9
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

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feat(mt8189): add EC pin control in SPM

Set EC pin control low/high when SPM suspend/resume.

Signed-off-by: Kun Lu <kun.lu@mediatek.com>
Change-Id: Id3360744e52cdcf5613e653cc831740a54140ee4

feat(mt8189): add LPM v2 support

Add LPM (Low Power Module) v2 support for MT8189. LPM connects idle and
SPM to achieve lower power consumption in some scenarios.

Signed-off-by: Kun Lu <kun.lu@medi

feat(mt8189): add LPM v2 support

Add LPM (Low Power Module) v2 support for MT8189. LPM connects idle and
SPM to achieve lower power consumption in some scenarios.

Signed-off-by: Kun Lu <kun.lu@mediatek.com>
Change-Id: Iacb23acd1848a57a6a140a47e030b235cfc43068

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feat(mt8189): add SPM common driver support

This patch mainly initializes the SPM and provides common APIs for SPM
to enable the use of its various features.

Signed-off-by: Kun Lu <kun.lu@mediatek.

feat(mt8189): add SPM common driver support

This patch mainly initializes the SPM and provides common APIs for SPM
to enable the use of its various features.

Signed-off-by: Kun Lu <kun.lu@mediatek.com>
Change-Id: I2b60cc18eafeb21ed08194315f781209a75f2dd7

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feat(mt8189): add VCORE DVFS drivers

VCORE DVFS is the feature to change VCORE/DDR Freq for power saving
When there are no requests for using VCORE/DRAM, VCORE DVFS will
lower the voltage and freque

feat(mt8189): add VCORE DVFS drivers

VCORE DVFS is the feature to change VCORE/DDR Freq for power saving
When there are no requests for using VCORE/DRAM, VCORE DVFS will
lower the voltage and frequency of VCORE/DRAM to achieve power saving.

Signed-off-by: Kun Lu <kun.lu@mediatek.com>
Change-Id: I625e9498c801092a1b2ed9844fe74357c0adaf96

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feat(mt8189): add SPM basic features support

This patch mainly collects and organizes SPM state information to
facilitate debugging when issues arise.

Signed-off-by: Kun Lu <kun.lu@mediatek.com>
Ch

feat(mt8189): add SPM basic features support

This patch mainly collects and organizes SPM state information to
facilitate debugging when issues arise.

Signed-off-by: Kun Lu <kun.lu@mediatek.com>
Change-Id: I477143c2003ed28040a4c8321bb89f81e6cc49db

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feat(mt8189): add SPM features support

When the system is in idle or suspend state, SPM will turn off some
unused system resources. This patch enables this feature to achieve
power saving.

Signed-o

feat(mt8189): add SPM features support

When the system is in idle or suspend state, SPM will turn off some
unused system resources. This patch enables this feature to achieve
power saving.

Signed-off-by: Kun Lu <kun.lu@mediatek.com>
Change-Id: Ia346c0ea94fa7e427b16c3071ce4eeaa329aab44

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feat(mt8189): enable PMIC low power setting

During suspend, it is necessary to set some power rails of the PMIC
to enter lower poewer mode to achieve power saving.

Signed-off-by: Kun Lu <kun.lu@med

feat(mt8189): enable PMIC low power setting

During suspend, it is necessary to set some power rails of the PMIC
to enter lower poewer mode to achieve power saving.

Signed-off-by: Kun Lu <kun.lu@mediatek.com>
Change-Id: I922d4f490ecc4db2a7825989d14b62a79f96f80e

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feat(mt8196): extract common SPM code for reuse

To promote code reuse and maintainability, move partial SPM driver to
common.

Signed-off-by: Kun Lu <kun.lu@mediatek.com>
Change-Id: I155e86758a14acb

feat(mt8196): extract common SPM code for reuse

To promote code reuse and maintainability, move partial SPM driver to
common.

Signed-off-by: Kun Lu <kun.lu@mediatek.com>
Change-Id: I155e86758a14acbce76c3b82f7d5b43eeaeca416

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fix(intel): add memory alignment at cadence SD/eMMC driver's descriptor

When compile using arm gcc compiler with versions 12 above,
the cadence SD/eMMC driver will failed with ADMA error. When
sendi

fix(intel): add memory alignment at cadence SD/eMMC driver's descriptor

When compile using arm gcc compiler with versions 12 above,
the cadence SD/eMMC driver will failed with ADMA error. When
sending MMC command. The memory is not aligned correctly
when using different version of gcc.

The descriptor memory must be aligned to 4 byte boundary
with 2 least significant bits set to 0 in 32-bit ADMA
addressing mode and aligned to 8 byte boundary with
3 least significant bits set to 0 in 64-bit ADMA
addresing mode.

Since 8 byte boundary is common to both 4 byte and
8 byte boundary hence aligning the descriptor
memory with 8 byte boundary.

Change-Id: Ie56d2aef22b4e4ef0fa516b9cda53b33d6316cb7
Signed-off-by: Boon Khai Ng <boon.khai.ng@altera.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>

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fix(console): create unique variable name

This corrects the MISRA violation C2012-5.7:
A tag name shall be a unique identifier.
Renamed the variable to ensure uniqueness.

Change-Id: I96e61caa8c6c7f

fix(console): create unique variable name

This corrects the MISRA violation C2012-5.7:
A tag name shall be a unique identifier.
Renamed the variable to ensure uniqueness.

Change-Id: I96e61caa8c6c7ff64759363afd24fc224d449f86
Signed-off-by: Nithin G <nithing@amd.com>
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>

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refactor(gicv3): clarify redistributor base address usage with USE_GIC_DRIVER=3

The GICv3 driver has 2 methods of discovering the redistributors:
a) via setting gicr_base - done at boot and assumes

refactor(gicv3): clarify redistributor base address usage with USE_GIC_DRIVER=3

The GICv3 driver has 2 methods of discovering the redistributors:
a) via setting gicr_base - done at boot and assumes all GICR frames are
contiguous. This is the original method.

b) via gicv3_rdistif_probe() - called from platform code and requires
gicr_base == 0. It relaxes the requirement for frames to be
contiguous, like in a multichip configuration, and defers the
discovery to core bringup. This was introduced later.

Configurations possible with option a) are also possible with option b)
with only slightly different behaviour. USE_GIC_DRIVER=3 inherited
option b) from plat_gicv3_base.c and as such option a) is unusable.
However, it is unclear from code how this should be used. Clarify this
by requiring platforms initialise with gic_set_gicr_frames() and
adding relevant comments.

Also rename plat_arm_override_gicr_frames() to gic_set_gicr_frames() as
this is not plat arm specific and a part of the generic GIC driver.

Change-Id: I61d77211f8e65dc54cf9904069b500d26a06b5a5
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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fix(gicv3): remove plat_gicv3_base.c

All platforms that used to use plat_gicv3_base.c have been ported to
USE_GIC_DRIVER=3 so this file is now unused. As USE_GIC_DRIVER is based
on plat_gicv3_base.c

fix(gicv3): remove plat_gicv3_base.c

All platforms that used to use plat_gicv3_base.c have been ported to
USE_GIC_DRIVER=3 so this file is now unused. As USE_GIC_DRIVER is based
on plat_gicv3_base.c and includes its own hooks, platforms should use
USE_GIC_DRIVER instead.

Change-Id: I9cb5c1fa881e7aed3de272d4482039bf112e60d8
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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refactor(versal-net): use the generic GIC driver

With the introduction of USE_GIC_DRIVER, platforms no longer have to do
their own GIC management for basic PSCI-related operations. Previously a
half

refactor(versal-net): use the generic GIC driver

With the introduction of USE_GIC_DRIVER, platforms no longer have to do
their own GIC management for basic PSCI-related operations. Previously a
half-measure was possible by using plat_gicv3_base.c to get semi-generic
helpers which versal_net uses.

Since USE_GIC_DRIVER is based on plat_gicv3_base.c, convert the platform
to use that so its code is more generic. Expected benefits are slightly
better performance around calling the gic hooks on cpu suspend and less
platform code.

Change-Id: I8e8a92fd4111e4a83c7a34bc5255d924bc54e769
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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Merge "feat(mt8189): fix the typo in the display driver" into integration

fix(intel): solve agilex warm reset issue

Agilex warm reset not able to trigger due to the system not able to
detect the magic number. ATF only able to solve for boot core.
For secondary cores, Linu

fix(intel): solve agilex warm reset issue

Agilex warm reset not able to trigger due to the system not able to
detect the magic number. ATF only able to solve for boot core.
For secondary cores, Linux need to update psci driver to WFI
the cores in EL3. Original Linux WFI is EL1.
Thus causing secondary cores not working

Change-Id: I5470abc19a09e45f16c4cd0049dd20e6534435bb
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>

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feat(mt8189): fix the typo in the display driver

Fix the typo for definition.

Signed-off-by: Xiandong Wang <xiandong.wang@mediatek.com>
Change-Id: I3e01bae3ba22c0ca00e76cd80d5f75b14e3115e2

fix(intel): support DDR In-line and Out-of-Band ECC handling

Enable the DDR ECC feature, initialize the memory based on
the ECC type (in-line or out-of-band), detect the DBE errors
and recover the s

fix(intel): support DDR In-line and Out-of-Band ECC handling

Enable the DDR ECC feature, initialize the memory based on
the ECC type (in-line or out-of-band), detect the DBE errors
and recover the system accordingly.

Change-Id: I5138124e0d68dc8c93c98ae71eb13a77e49fd682
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>

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feat(intel): move common functions to common lib files

This patch is used to move common functions that used across
files into commmon lib files to prevent multiple functions
declaration and share a

feat(intel): move common functions to common lib files

This patch is used to move common functions that used across
files into commmon lib files to prevent multiple functions
declaration and share among files.

Change-Id: I19d9727eac895e7bf597a66076a7b68755cbe0ef
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>

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