| 32669476 | 09-Dec-2020 |
Pankaj Gupta <pankaj.gupta@nxp.com> |
nxp-tool: for creating pbl file from bl2
NXP tool to create pbl from bl2 binary: - RCW is prepended to BL2.bin - If TRUSTED_BOARD_BOOT=1, pre-append the CSF header to be understood by NXP boot-rom.
nxp-tool: for creating pbl file from bl2
NXP tool to create pbl from bl2 binary: - RCW is prepended to BL2.bin - If TRUSTED_BOARD_BOOT=1, pre-append the CSF header to be understood by NXP boot-rom.
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com> Change-Id: Iddc7336a045222e2073ddad86358ebc4440b8bcf
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| 39faa9b2 | 09-Dec-2020 |
Pankaj Gupta <pankaj.gupta@nxp.com> |
nxp: adding the smmu driver
NXP SMMU driver API for NXP SoC. - Currently it supports by-passing SMMU, called only when NXP CAAM is enabled. - (TBD) AMQ based SMMU access control: Access Management Q
nxp: adding the smmu driver
NXP SMMU driver API for NXP SoC. - Currently it supports by-passing SMMU, called only when NXP CAAM is enabled. - (TBD) AMQ based SMMU access control: Access Management Qualifiers (AMQ) advertised by a bus master for a given transaction.
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com> Change-Id: I23a12928ddedb1a2cf4b396606e35c67e016e331
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| 35988193 | 09-Dec-2020 |
Pankaj Gupta <pankaj.gupta@nxp.com> |
nxp: cot using nxp internal and mbedtls
Chain of trust(CoT) is enabled on NXP SoC in two ways: - Using MbedTLS, parsing X509 Certificates. - Using NXP internal method parsing CSF header
Signed-off-
nxp: cot using nxp internal and mbedtls
Chain of trust(CoT) is enabled on NXP SoC in two ways: - Using MbedTLS, parsing X509 Certificates. - Using NXP internal method parsing CSF header
Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com> Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com> Change-Id: I78fb28516dfcfa667bebf8a1951ffb24bcab8de4
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| a0edacb8 | 09-Dec-2020 |
Pankaj Gupta <pankaj.gupta@nxp.com> |
nxp:driver for crypto h/w accelerator caam
NXP has hardware crypto accelerator called CAAM. - Work with Job ring - Jobs are submitted to CAAM in the form of 64 word descriptor.
Signed-off-by: Ruc
nxp:driver for crypto h/w accelerator caam
NXP has hardware crypto accelerator called CAAM. - Work with Job ring - Jobs are submitted to CAAM in the form of 64 word descriptor.
Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com> Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com> Change-Id: I02bcfce68143b8630e1833a74c4b126972f4323d
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| 066ee1ad | 09-Dec-2020 |
Pankaj Gupta <pankaj.gupta@nxp.com> |
nxp:add driver support for sd and emmc
SD & eMMC driver support for NXP SoC.
Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com> Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com> Change-Id: I245f
nxp:add driver support for sd and emmc
SD & eMMC driver support for NXP SoC.
Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com> Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com> Change-Id: I245fecd2c791697238b5667c46bf5466379695ce
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| c20e123c | 09-Dec-2020 |
Pankaj Gupta <pankaj.gupta@nxp.com> |
nxp:add qspi driver
NXP QuadSPI driver support NXP SoC. - Supporting QSPI flash
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com> Change-Id: I928cbec8ea31f4d8f9e320ac9c5105f7ab0ecb73 |
| b525a8f0 | 09-Dec-2020 |
Kuldeep Singh <kuldeep.singh@nxp.com> |
nxp: add flexspi driver support
Flexspi driver now introduces read/write/erase APIs for complete flash size, FAST-READ are by default used and IP bus is used for erase, read and write using flexspi
nxp: add flexspi driver support
Flexspi driver now introduces read/write/erase APIs for complete flash size, FAST-READ are by default used and IP bus is used for erase, read and write using flexspi APIs.
Framework layer is currently embedded in driver itself using flash_info defines.
Test cases are also added to confirm flash functionality currently under DEBUG flag.
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com> Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com> Change-Id: I755c0f763f6297a35cad6885f84640de50f51bb0
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| b53334da | 09-Dec-2020 |
Pankaj Gupta <pankaj.gupta@nxp.com> |
nxp: adding gic apis for nxp soc
GIC api used by NXP SoC is based on: - arm provided drivers: /drivers/arm/gic
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com> Change-Id: If3d470256e5bd078614f191
nxp: adding gic apis for nxp soc
GIC api used by NXP SoC is based on: - arm provided drivers: /drivers/arm/gic
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com> Change-Id: If3d470256e5bd078614f191e56062c4fbd97f8bd
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| e3e48b5c | 09-Dec-2020 |
Pankaj Gupta <pankaj.gupta@nxp.com> |
nxp: gpio driver support
NXP General Purpose Input/Output driver support for NXP platforms.
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com> Change-Id: I9a3574f1d5d12e4a65ff60f640d4e77e2defd6d4 |
| 34412eda | 09-Dec-2020 |
Pankaj Gupta <pankaj.gupta@nxp.com> |
nxp: added csu driver
NXP Central Security Unit(CSU) for NXP SoC. CSU is used for: - Access permissions for peripheral that donot have their own access control. - Locking of individual CSU setting
nxp: added csu driver
NXP Central Security Unit(CSU) for NXP SoC. CSU is used for: - Access permissions for peripheral that donot have their own access control. - Locking of individual CSU settings until the next POR - General purpose security related control bits
Refer NXP SoC manuals fro more details.
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com> Change-Id: I07a4729c79c5e2597f8b2a782e87e09f7f30c2ca
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| d57186ea | 09-Dec-2020 |
Pankaj Gupta <pankaj.gupta@nxp.com> |
nxp: driver pmu for nxp soc
Driver for NXP IP for Power Management Unit.
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com> Change-Id: I855657eddab357cb182419b188ed8861c46a1b19 |
| b35ce0c4 | 09-Dec-2020 |
Pankaj Gupta <pankaj.gupta@nxp.com> |
nxp: ddr driver enablement for nxp layerscape soc
DDR driver for NXP layerscape SoC(s): - lx2160aqds - lx2162aqds - lx2160ardb - Other Board with SoC(s) like ls1046a, ls1043a etc; -- These othe
nxp: ddr driver enablement for nxp layerscape soc
DDR driver for NXP layerscape SoC(s): - lx2160aqds - lx2162aqds - lx2160ardb - Other Board with SoC(s) like ls1046a, ls1043a etc; -- These other boards are not verified yet.
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: York Sun <york.sun@nxp.com> Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com> Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com> Change-Id: Ic84a63cb30eba054f432d479862cd4d1097cbbaf
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| c6d9fdbc | 09-Dec-2020 |
Pankaj Gupta <pankaj.gupta@nxp.com> |
nxp: i2c driver support.
NXP I2C driver support for NXP SoC(s).
Signed-off-by: York Sun <york.sun@nxp.com> Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com> Change-Id: I234b76f9fa1b30dd13aa0870014
nxp: i2c driver support.
NXP I2C driver support for NXP SoC(s).
Signed-off-by: York Sun <york.sun@nxp.com> Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com> Change-Id: I234b76f9fa1b30dd13aa087001411370cc6c8dd0
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| d8e97999 | 09-Dec-2020 |
Pankaj Gupta <pankaj.gupta@nxp.com> |
NXP: Driver for NXP Security Monitor
NXP Security Monitor IP provides hardware anchored - current security state of the SoC. - Tamper detect etc.
Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com
NXP: Driver for NXP Security Monitor
NXP Security Monitor IP provides hardware anchored - current security state of the SoC. - Tamper detect etc.
Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com> Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com> Change-Id: I8ff809fe2f3fd013844ab3d4a8733f53c2b06c81
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| 3979c6d9 | 09-Dec-2020 |
Pankaj Gupta <pankaj.gupta@nxp.com> |
NXP: SFP driver support for NXP SoC
NXP Security Fuse Processor is used to read and write fuses. - Fuses once written, are cannot be un-done. - Used as trust anchor for monotonic counter, differen
NXP: SFP driver support for NXP SoC
NXP Security Fuse Processor is used to read and write fuses. - Fuses once written, are cannot be un-done. - Used as trust anchor for monotonic counter, different platform keys etc.
Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com> Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com> Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com> Change-Id: I347e806dd87078150fbbbfc28355bb44d9eacb9c
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| 76f735fd | 09-Dec-2020 |
Pankaj Gupta <pankaj.gupta@nxp.com> |
NXP: Interconnect API based on ARM CCN-CCI driver
CCN API(s) to be used NXP SoC(s) are added. These API(s) based on ARM CCN driver - driver/arm/ccn
CCI API(s) to be used NXP SoC(s) are added. These
NXP: Interconnect API based on ARM CCN-CCI driver
CCN API(s) to be used NXP SoC(s) are added. These API(s) based on ARM CCN driver - driver/arm/ccn
CCI API(s) to be used NXP SoC(s) are added. These API(s) based on ARM CCI driver - driver/arm/cci
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com> Change-Id: I7682c4c9bd42f63542b3ffd3cb6c5d2effe4ae0a
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| de0b1012 | 09-Dec-2020 |
Pankaj Gupta <pankaj.gupta@nxp.com> |
NXP: TZC API to configure ddr region
NXP TZC-400 API(s) to configure ddr regions are based on: - drivers/arm/tzc
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com> Change-Id: I524433ff9fafe1170b13e
NXP: TZC API to configure ddr region
NXP TZC-400 API(s) to configure ddr regions are based on: - drivers/arm/tzc
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com> Change-Id: I524433ff9fafe1170b13e99b7de01fe957b6d305
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| 447a42e7 | 09-Dec-2020 |
Pankaj Gupta <pankaj.gupta@nxp.com> |
NXP: Timer API added to enable ARM generic timer
NXP Timer Apis are based on: - drivers/delay_timer
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com> Change-Id: I2cbccf4c082a10affee1143390905b9cc9
NXP: Timer API added to enable ARM generic timer
NXP Timer Apis are based on: - drivers/delay_timer
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com> Change-Id: I2cbccf4c082a10affee1143390905b9cc99c3382
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| 86b1b89f | 09-Dec-2020 |
Pankaj Gupta <pankaj.gupta@nxp.com> |
nxp: add dcfg driver
NXP SoC needs Device Configuration driver to fetch the current SoC configuration.
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com> Change-Id: Ie17cca01a8eb9a6f5feebb093756f57
nxp: add dcfg driver
NXP SoC needs Device Configuration driver to fetch the current SoC configuration.
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com> Change-Id: Ie17cca01a8eb9a6f5feebb093756f577692432bf
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| 0499215e | 09-Dec-2020 |
Pankaj Gupta <pankaj.gupta@nxp.com> |
nxp:add console driver for nxp platform
NXP SoCs, supports two types of UART controller: - PL011 - using ARM drivers sources - 16550 - using TI drivers source
Signed-off-by: Pankaj Gupta <pankaj.gu
nxp:add console driver for nxp platform
NXP SoCs, supports two types of UART controller: - PL011 - using ARM drivers sources - 16550 - using TI drivers source
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com> Change-Id: Iacbcefd2b6e5d96f83fa00ad25b4f63a4c822bb4
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| 3527d6d2 | 09-Dec-2020 |
Pankaj Gupta <pankaj.gupta@nxp.com> |
tools: add mechanism to allow platform specific image UUID
Generic framework is added to include platform defined UUID.
This framework is added for the following: - All NXP SoC based platforms need
tools: add mechanism to allow platform specific image UUID
Generic framework is added to include platform defined UUID.
This framework is added for the following: - All NXP SoC based platforms needed additional fip-fuse.bin - NXP SoC lx2160a based platforms requires additional fip-ddr.bin
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com> Change-Id: Ibe05d9c596256e34077287a490dfcd5b731ef2cf
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| 18644159 | 09-Dec-2020 |
Pankaj Gupta <pankaj.gupta@nxp.com> |
tbbr-cot: conditional definition for the macro
Conditional definition for the macro MAX_NUMBER_IDS.
This will allow to update this definition by the platform specific implementation.
Since, NXP So
tbbr-cot: conditional definition for the macro
Conditional definition for the macro MAX_NUMBER_IDS.
This will allow to update this definition by the platform specific implementation.
Since, NXP SoC lx2160a based platforms requires additional FIP DDR to be loaded before initializing the DDR.
It requires addition of defines for DDR image IDs. A dedicated header plat_tbbr_img_def.h is added to the platform folder - plat/nxp/common/include/default/
Inclusion of this header file will depend on the compile time flag PLAT_TBBR_IMG_DEF.
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com> Change-Id: I4faba74dce578e2a34acbc8915ff75d7b8368cee
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| ff67fca5 | 09-Dec-2020 |
Pankaj Gupta <pankaj.gupta@nxp.com> |
tbbr-cot: fix the issue of compiling time define
Incorrect value is picked for TF_MBEDTLS_USE_RSA defination, even if the TF_MBEDTLS_RSA is enabled.
Due to which PK_DER_LEN is defined incorrectly.
tbbr-cot: fix the issue of compiling time define
Incorrect value is picked for TF_MBEDTLS_USE_RSA defination, even if the TF_MBEDTLS_RSA is enabled.
Due to which PK_DER_LEN is defined incorrectly.
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com> Change-Id: I2ca4ca121e0287b88ea689c885ddcd45a34a3e91
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| b94bf967 | 09-Dec-2020 |
Pankaj Gupta <pankaj.gupta@nxp.com> |
cert_create: updated tool for platform defined certs, keys & extensions
Changes to 'tools/cert_create' folder, to include platform defined certificates, keys, and extensions.
NXP SoC lx2160a : base
cert_create: updated tool for platform defined certs, keys & extensions
Changes to 'tools/cert_create' folder, to include platform defined certificates, keys, and extensions.
NXP SoC lx2160a : based platforms requires additional FIP DDR to be loaded before initializing the DDR.
To enable chain of trust on these platforms, FIP DDR image needs to be authenticated, additionally.
Platform specific folder 'tools/nxp/cert_create_helper' is added to support platform specific macros and definitions.
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com> Change-Id: I4752a30a9ff3aa1d403e9babe3a07ba0e6b2bf8f
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| 6c74c997 | 26-Jan-2021 |
Pankaj Gupta <pankaj.gupta@nxp.com> |
tbbr-tools: enable override TRUSTED_KEY_CERT
Platforms, which requires additional images to be verified using TBBR; such that their key certificate is tied to TRUSTED_KEY_CERT.
For such platforms,
tbbr-tools: enable override TRUSTED_KEY_CERT
Platforms, which requires additional images to be verified using TBBR; such that their key certificate is tied to TRUSTED_KEY_CERT.
For such platforms, if make commands runs twice: - Once with targets as bl2 & fip.bin, and - Again to build the target as the additional image.
then, if path to the TRUSTED_KEY_CERT varies in the makefile with make-target of the additional image, then there would be two location where "trusted_key.crt" will be created.
This patch helps overriding the TRUSTED_KEY_CERT from any .mk in the platform's makefile structure.
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com> Change-Id: I775a2c409035504b21b0bbe5a4f9046898163eed
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