docs(versal): update custom SIP service

Correct the platform-specific custom SiP service doc
VERSAL_SIP_SVC_CUSTOM to use the common SOC_SIP_SVC_CUSTOM.

Change-Id: Iab75295432aec1329d3aa69f30897c8a

docs(versal): update custom SIP service

Correct the platform-specific custom SiP service doc
VERSAL_SIP_SVC_CUSTOM to use the common SOC_SIP_SVC_CUSTOM.

Change-Id: Iab75295432aec1329d3aa69f30897c8aaa5a7b9e
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>

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fix(versal-net): add fallback on handoff failure

On the Versal-Net platform, booting can fail during ELF loading due to
the absence of a PLM handoff, preventing the system from booting
further.

To

fix(versal-net): add fallback on handoff failure

On the Versal-Net platform, booting can fail during ELF loading due to
the absence of a PLM handoff, preventing the system from booting
further.

To address this, a fallback mechanism has been introduced that allows
the boot process to continue even if the PLM handoff is not provided
only in debug builds with jtag boot mode.

Change-Id: Ib8d92ab8400b7a63b05ae8c77b40b30fe7abaab8
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>

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fix(psci): initialize the variables

This corrects the MISRA violation C2012-9.1:
All variables are explicitly initialized with zero or default values
during declaration. This helps, even if a functi

fix(psci): initialize the variables

This corrects the MISRA violation C2012-9.1:
All variables are explicitly initialized with zero or default values
during declaration. This helps, even if a function fails, the
variables contain predictable values, preventing undefined behavior

Change-Id: I910467fd03e434e32da01e421fe77ec1402bc15a
Signed-off-by: Saivardhan Thatikonda <saivardhan.thatikonda@amd.com>

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feat(mt8189): add mt8189 mtcmos platform data

Add mt8189 mtcmos platform data.

Signed-off-by: irving-ch-lin <irving-ch.lin@mediatek.com>
Change-Id: I8c979522c6105faac40e0e8f5438718063eba1a4

refactor(mt8196): refactor mtcmos driver to support per platform data

Change for seperating platform in mtcmos control:
1. Pass bus protect steps table to spm_mtcmos_ctrl_bus_prot
2. Pass has_sram f

refactor(mt8196): refactor mtcmos driver to support per platform data

Change for seperating platform in mtcmos control:
1. Pass bus protect steps table to spm_mtcmos_ctrl_bus_prot
2. Pass has_sram flags for sram control
3. Use rtff_save_flag for chip without hw RTFF_SAVE_FLAG

Add mt8196 platform data:
1. RTFF related control bit in register
2. PWR_CON address
3. bus protect steps tables

Signed-off-by: irving-ch-lin <irving-ch.lin@mediatek.com>
Change-Id: I7b39bf5b590cc5cc53f4f3625a7d5a7b4de7cdcb

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feat(mt8189): add mcdi driver

Minor hardware changes require minor driver updates.

Signed-off-by: Kai Liang <kai.liang@mediatek.corp-partner.google.com>
Change-Id: Ifd8f248f0ab18a5e6a4e27fce3b3f345

feat(mt8189): add mcdi driver

Minor hardware changes require minor driver updates.

Signed-off-by: Kai Liang <kai.liang@mediatek.corp-partner.google.com>
Change-Id: Ifd8f248f0ab18a5e6a4e27fce3b3f345bb50d901

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Merge "fix(docs): obey the build directory" into integration

Merge "chore(deps): add LTS-v2.12 Dependabot configuration" into integration

Merge changes Iab4a77a6,I38c32fa3 into integration

* changes:
feat(mt8189): add support for PTP3
refactor(mediatek): move ptp3_plat.h to common code

fix(intel): select the DFI interface based on the hand-off data

Select the DFI interface based on the hand-off power
gate enable data, whether NAND or SDMMC controller is
selected based on this data

fix(intel): select the DFI interface based on the hand-off data

Select the DFI interface based on the hand-off power
gate enable data, whether NAND or SDMMC controller is
selected based on this data.

Change-Id: I097b7f84874368a5ed265d8fa7fff193f430b245
Signed-off-by: Girisha Dengi <girisha.dengi@altera.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>

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fix(intel): fix SDMMC driver when sdmclk running at 200MHz

When SDMMC sdmclk running at 200MHz setting the sdclk
to 25MHz will fail. so setting the sdclk to 50MHz for
SDMMC.

Change-Id: I56398893717

fix(intel): fix SDMMC driver when sdmclk running at 200MHz

When SDMMC sdmclk running at 200MHz setting the sdclk
to 25MHz will fail. so setting the sdclk to 50MHz for
SDMMC.

Change-Id: I56398893717afe1fa0de167aae532f8b8de03b1c
Signed-off-by: Boon Khai Ng <boon.khai.ng@altera.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>

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fix(intel): fix eMMC driver issues in boot flow on agilex5

Fixed issue where reading the EXT_CSD register via CMD8
with DMA enabled returned 0 value. Updated the read mode
to handle this case correc

fix(intel): fix eMMC driver issues in boot flow on agilex5

Fixed issue where reading the EXT_CSD register via CMD8
with DMA enabled returned 0 value. Updated the read mode
to handle this case correctly.

Added polling for the ICS bit after enabling ICE when
setting the SDCLK rate. Introduced delay to ensure
proper clock stabilization.

Corrected SD_HOST_CLK to data driven from the clock manager
as sdmclk.

eMMC operates in legacy mode, which has a maximum
supported clock rate of 26 MHz. Updated the clock
setting to 25 MHz to meet this requirement.

Change-Id: I4ac2b9b69b5dec2c8166d06c736d9c2c549607de
Signed-off-by: Boon Khai Ng <boon.khai.ng@altera.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>

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fix(intel): fix iossm driver timeout in agilex5

bl2_plat_setup.c: check return value for
agilex5_ddr_init. If init fail, it will go into
panic. This will help future debug to root cause
the actual i

fix(intel): fix iossm driver timeout in agilex5

bl2_plat_setup.c: check return value for
agilex5_ddr_init. If init fail, it will go into
panic. This will help future debug to root cause
the actual issue.

agilex5_iossm_mailbox.c: corrected divisor
for read_count in inline_ecc_bist_mem_init. Wrong
divisor will cause read_count to be 0. The same
value is also used in out_of_band_ecc_bist_mem_init.

Change-Id: I4c85d251b7e88f3176902917450572adb574b33a
Signed-off-by: Goh Shun Jing <shun.jing.goh@altera.com>
Signed-off-by: Boon Khai Ng <boon.khai.ng@altera.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>

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fix(intel): set BIT2 of system manager MPFE Interface Select

Set BIT2 of system manager MPFE Interface Select register to
access the EMIF_1.

Change-Id: I6bb2776e5320bde326c6bf97cb785389cad5fb90
Sig

fix(intel): set BIT2 of system manager MPFE Interface Select

Set BIT2 of system manager MPFE Interface Select register to
access the EMIF_1.

Change-Id: I6bb2776e5320bde326c6bf97cb785389cad5fb90
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>

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fix(docs): obey the build directory

Like everything else, BUILD_BASE should be the canonical place to put
all output of a build.

Change-Id: Ibab9992550bb70fc0b71453ada37cdc94858f6fc
Signed-off-by:

fix(docs): obey the build directory

Like everything else, BUILD_BASE should be the canonical place to put
all output of a build.

Change-Id: Ibab9992550bb70fc0b71453ada37cdc94858f6fc
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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fix(intel): unexpected DDR reset type value observed on Agilex5

Redesign the reset type detection logic in the DDR driver.
Implement a more robust and comprehensive check that accurately
distinguish

fix(intel): unexpected DDR reset type value observed on Agilex5

Redesign the reset type detection logic in the DDR driver.
Implement a more robust and comprehensive check that accurately
distinguishes all possible DDR_RESET_TYPE values, including 0x4
and any future additions.

Change-Id: I8f1abdc8269b0de68733e5fcb3f12b4a5640770e
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>

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fix(intel): flush the mailbox response buffer in SiPSVC V3

In SiPSVC V3, the user suppiled buffer will be directly used
for collecting the response from SDM mailbox - this way we
can avoid keeping t

fix(intel): flush the mailbox response buffer in SiPSVC V3

In SiPSVC V3, the user suppiled buffer will be directly used
for collecting the response from SDM mailbox - this way we
can avoid keeping the response local copy in the TF-A and
improve performance. Once the response is collected in the
user buffer, we need to FLUSH to maintain coherency.

Change-Id: I265ce177fe42d7ab647c875d52286de4b998672d
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>

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fix(intel): update the RSU version logic read

Update the RSU version logic read, keep the version
with backward compatible as SiPSVC V1.

Change-Id: Ibb0f3bb631c7759e65ac028a9e52006f2f057e6f
Signed-

fix(intel): update the RSU version logic read

Update the RSU version logic read, keep the version
with backward compatible as SiPSVC V1.

Change-Id: Ibb0f3bb631c7759e65ac028a9e52006f2f057e6f
Signed-off-by: Girisha Dengi <girisha.dengi@altera.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>

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Merge changes I61d77211,I9cb5c1fa,I8e8a92fd into integration

* changes:
refactor(gicv3): clarify redistributor base address usage with USE_GIC_DRIVER=3
fix(gicv3): remove plat_gicv3_base.c
ref

Merge changes I61d77211,I9cb5c1fa,I8e8a92fd into integration

* changes:
refactor(gicv3): clarify redistributor base address usage with USE_GIC_DRIVER=3
fix(gicv3): remove plat_gicv3_base.c
refactor(versal-net): use the generic GIC driver

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feat(mt8189): add support for PTP3

Use common PTP3 driver to protect CPU from excessive voltage drop in CPU
heavy loading.

Signed-off-by: Hope Wang <hope.wang@mediatek.corp-partner.google.com>
Chan

feat(mt8189): add support for PTP3

Use common PTP3 driver to protect CPU from excessive voltage drop in CPU
heavy loading.

Signed-off-by: Hope Wang <hope.wang@mediatek.corp-partner.google.com>
Change-Id: Iab4a77a6d1816a520f3fe112ef94efdc5789f6c8

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refactor(mediatek): move ptp3_plat.h to common code

To improve code reusability, move the common code from
mt8188/ptp3_plat.h and mt8195/ptp3_plat.h into ptp3_common.h. Place the
platform-specific c

refactor(mediatek): move ptp3_plat.h to common code

To improve code reusability, move the common code from
mt8188/ptp3_plat.h and mt8195/ptp3_plat.h into ptp3_common.h. Place the
platform-specific code in ptp3_plat_v1.h for mt8195 and ptp3_plat_v2.h
for mt8188.

Signed-off-by: Hope Wang <hope.wang@mediatek.corp-partner.google.com>
Change-Id: I38c32fa3ad03f9dc7a653ed89da335d26f70f75b

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Merge "fix(intel): update generic mailbox command filter method" into integration

fix(intel): update generic mailbox command filter method

Update generic mailbox command filter method, filter the
commands based on the mailbox spec command ID and not on
the SMC function ID.

Chang

fix(intel): update generic mailbox command filter method

Update generic mailbox command filter method, filter the
commands based on the mailbox spec command ID and not on
the SMC function ID.

Change-Id: Icceecc4c41858254d1a44e83552561f0b7c313ac
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>

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Merge "fix(intel): add memory alignment at cadence SD/eMMC driver's descriptor" into integration

Merge "fix(intel): solve agilex warm reset issue" into integration