docs: spm design document refresh

General refresh of the SPM document.

Change-Id: I2f8e37c3f34bc8511b115f00b9a53b6a6ff41bea
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>

feat(tc0): add support for trusted services

This patch adds support for the crypto and secure storage secure
partitions for the Total Compute platform. These secure partitions
have to be managed by

feat(tc0): add support for trusted services

This patch adds support for the crypto and secure storage secure
partitions for the Total Compute platform. These secure partitions
have to be managed by Hafnium executing at S-EL2

Change-Id: I2df690e3a99bf6bf50e2710994a905914a07026e
Signed-off-by: Davidson K <davidson.kumaresan@arm.com>

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docs(release): add change log for v2.5 release

Change log for trusted-firmware-a v2.5 release

Change-Id: I6ffc8a40d2cc3a18145b87f895acdc1400db485a
Signed-off-by: Madhukar Pappireddy <madhukar.pappi

docs(release): add change log for v2.5 release

Change log for trusted-firmware-a v2.5 release

Change-Id: I6ffc8a40d2cc3a18145b87f895acdc1400db485a
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

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Merge "fix(plat/arm_fpga): increase initrd size" into integration

docs: add threat model code owners

Signed-off-by: Zelalem Aweke <zelalem.aweke@arm.com>
Change-Id: I97b2c5c5cfbf4ddb055d0f7a5ab04386460db060

Merge "docs: removing "upcoming" change log" into integration

docs: removing "upcoming" change log

Removing the "Upcoming" change log due to the change in change log
processing.

Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: I6d2cc0

docs: removing "upcoming" change log

Removing the "Upcoming" change log due to the change in change log
processing.

Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: I6d2cc095dca3e654bd7e6fec2077c58bfbc48bb5

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fix(plat/arm_fpga): increase initrd size

In the comment in the ARM FPGA DT we promise a generous 100 MB initrd,
but actually describe only a size of 20 MB.

As initrds are the most common and easy u

fix(plat/arm_fpga): increase initrd size

In the comment in the ARM FPGA DT we promise a generous 100 MB initrd,
but actually describe only a size of 20 MB.

As initrds are the most common and easy userland option for the boards,
let's increase the maximum size to the advertised 100 MB, to avoid
unpacking errors when an initrd exceeds the current limit of 20 MB.

Change-Id: If08ba3fabdad27b2c2aff93b18c3f664728b4348
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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Merge "docs: revert FVP versions for select models" into integration

docs: revert FVP versions for select models

Reverting FVP versions to previous version 11.12.38 for Cortex-A32x4
and Neoverse-N2x4.

Change-Id: I81e8ad24794dd425a9e9a66dc8bb02b42191abf1
Signed-off-b

docs: revert FVP versions for select models

Reverting FVP versions to previous version 11.12.38 for Cortex-A32x4
and Neoverse-N2x4.

Change-Id: I81e8ad24794dd425a9e9a66dc8bb02b42191abf1
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>

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fix(services): drop warning on unimplemented calls

Standard Secure Services, complying to the SMCCC specification, are
discoverable: Any user can do the SMC call, and derive from the return
value (-

fix(services): drop warning on unimplemented calls

Standard Secure Services, complying to the SMCCC specification, are
discoverable: Any user can do the SMC call, and derive from the return
value (-1) if the service is implemented. Consequently we should not
*warn* if BL31 does not implement a service, as some services (TRNG, for
instance) might never be implemented for devices, as they are lacking
hardware.

Short of dropping the existing warning message altogether, change the
level to VERBOSE, which should prevent it actually being printed in
normal situations.

This removes the pointless TF-A messages on the console when booting
Linux, as modern kernels now call the SOCID and the TRNG service
unconditionally.

Change-Id: I08b0b02e0f46322ebe0b40b3991c3c9b5bed4f97
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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feat(plat/sgi): enable AMU for RD-V1-MC

AMU counters are used for monitoring the CPU performance. RD-V1-MC
platform has architected AMU available for each core. Enable the use of
AMU by non-secure O

feat(plat/sgi): enable AMU for RD-V1-MC

AMU counters are used for monitoring the CPU performance. RD-V1-MC
platform has architected AMU available for each core. Enable the use of
AMU by non-secure OS for supporting the use of counters for processor
performance control (ACPI CPPC).

Change-Id: I33be594cee669e7f4031e5e5a371eec7c7451030
Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>

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Merge "docs: update list of supported FVP platforms" into integration

Merge "docs(threat model): add TF-A threat model" into integration

docs(threat model): add TF-A threat model

This is the first release of the public Trusted
Firmware A class threat model. This release
provides the baseline for future updates to be
applied as requir

docs(threat model): add TF-A threat model

This is the first release of the public Trusted
Firmware A class threat model. This release
provides the baseline for future updates to be
applied as required by developments to the
TF-A code base.

Signed-off-by: Zelalem Aweke <zelalem.aweke@arm.com>
Change-Id: I3c9aadc46196837679f0b1377bec9ed4fc42ff11

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docs: update list of supported FVP platforms

Updated the list of supported FVP platforms as per the latest FVP
release.

Change-Id: I1abd0a7885b1133715062ee1b176733556a4820e
Signed-off-by: Lauren We

docs: update list of supported FVP platforms

Updated the list of supported FVP platforms as per the latest FVP
release.

Change-Id: I1abd0a7885b1133715062ee1b176733556a4820e
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>

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Merge "plat/st: do not rely on tainted value for dt property length" into integration

Merge changes from topic "imx8mp_fix" into integration

* changes:
plat: imx8mp: change the bl31 physical load address
plat: imx8m: Fix the macro define error

plat: imx8mp: change the bl31 physical load address

on i.MX8MP A1 silicon, the OCRAM space is extended to 512K + 64K,
currently, OCRAM @0x960000-0x980000 is reserved for BL31, it will
leave the last

plat: imx8mp: change the bl31 physical load address

on i.MX8MP A1 silicon, the OCRAM space is extended to 512K + 64K,
currently, OCRAM @0x960000-0x980000 is reserved for BL31, it will
leave the last 64KB in non-continuous space. To provide a continuous
384KB + 64KB space for generic use, so move the BL31 space to
0x970000-0x990000 range.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I96d572fc0f87f05a60f55e0552a68b6e70f8e7f4

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plat: imx8m: Fix the macro define error

the 'always_on' member should be initialized from 'on'.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I5746ff40075b4fcda2ac7d04a8d7f1269af17e91

Merge changes I8e67a921,I0dc06072,I5e149063,I962cdfc7,I5c5d0444 into integration

* changes:
plat: ti: k3: board: Let explicitly map our SEC_SRAM_BASE to 0x0
plat: ti: k3: board: Lets cast our ma

Merge changes I8e67a921,I0dc06072,I5e149063,I962cdfc7,I5c5d0444 into integration

* changes:
plat: ti: k3: board: Let explicitly map our SEC_SRAM_BASE to 0x0
plat: ti: k3: board: Lets cast our macros
plat: ti: k3: common: bl31_setup: Use BL31_SIZE instead of computing
plat: ti: k3: platform_def.h: Define the correct number of max table entries
plat: ti: k3: board: lite: Increase SRAM size to account for additional table

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Merge "feat(tc0): update Matterhorn ELP DVFS clock index" into integration

feat(tc0): update Matterhorn ELP DVFS clock index

This allows the the Matterhorn ELP Arm core to operate at its
designated OPP.

Signed-off-by: Usama Arif <usama.arif@arm.com>
Change-Id: I7ccef0cfd0

feat(tc0): update Matterhorn ELP DVFS clock index

This allows the the Matterhorn ELP Arm core to operate at its
designated OPP.

Signed-off-by: Usama Arif <usama.arif@arm.com>
Change-Id: I7ccef0cfd079d630c3cfe7874590bf42789a1dca

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Merge "docs: remove PSA wording for SPM chapters" into integration

Merge "revert(commitlint): disable `signed-off-by` rule" into integration