perf(spmd): omit sel1 context save if sel2 present

The SPMC at S-EL2 manages S-EL1 execution contexts for SPs. The
currently running SP vCPU state is always saved when the SPMC exits to
SPMD. A fres

perf(spmd): omit sel1 context save if sel2 present

The SPMC at S-EL2 manages S-EL1 execution contexts for SPs. The
currently running SP vCPU state is always saved when the SPMC exits to
SPMD. A fresh vCPU context is always restored when the SPMC is entered
from the SPMD and a SP resumed. For performance optimization reasons
this permits omitting the saving/restoring of the S-EL1 context from
within the EL3 SPMD on entering/exiting the SPMC. The S-EL2 SPMC and
NS-EL1 context save/restore remain done in the SPMD.

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I66413ed5983913791ff5c9fc03c590ee65c6ccd7

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fix(fvp): spmc optee manifest remove SMC allowlist

Fix a remainder from early prototyping. OP-TEE as a secure partition
does not need specific SMC function id pass through to EL3.

Signed-off-by: Ol

fix(fvp): spmc optee manifest remove SMC allowlist

Fix a remainder from early prototyping. OP-TEE as a secure partition
does not need specific SMC function id pass through to EL3.

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I2843d1b9a5eb4c966f82790e1655fb569c2de7d4

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fix: random typos in tf-a code base

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: Id610f7e4398e799a2fbd74861274fd684c32db53

Merge "fix(plat/arm): correct UUID strings in FVP DT" into integration

fix(plat/arm): correct UUID strings in FVP DT

The UUID strings used in FW_CONFIG DT are not aligned with UUIDs defined
in include/tools_share/firmware_image_package.h for BL32_EXTRA1 and
TRUSTED_KEY

fix(plat/arm): correct UUID strings in FVP DT

The UUID strings used in FW_CONFIG DT are not aligned with UUIDs defined
in include/tools_share/firmware_image_package.h for BL32_EXTRA1 and
TRUSTED_KEY_CERT.

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: I517f8f9311585931f2cb931e0588414da449b694

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Merge "feat(plat/imx8m): add SiP call for secondary boot" into integration

fix(plat/marvell/a3720/uart): fix UART parent clock rate determination

The UART code for the A3K platform assumes that UART parent clock rate
is always 25 MHz. This is incorrect, because the xtal cl

fix(plat/marvell/a3720/uart): fix UART parent clock rate determination

The UART code for the A3K platform assumes that UART parent clock rate
is always 25 MHz. This is incorrect, because the xtal clock can also run
at 40 MHz (this is board specific).

The frequency of the xtal clock is determined by a value on a strapping
pin during SOC reset. The code to determine this frequency is already in
A3K's comphy driver.

Move the get_ref_clk() function from the comphy driver to a separate
file and use it for UART parent clock rate determination.

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I8bb18a2d020ef18fe65aa06ffa4ab205c71be92e

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docs: change Linaro release version to 20.01

We currently use Linaro release software stack version
20.01 in the CI. Reflect that change in the docs.

Signed-off-by: Zelalem Aweke <zelalem.aweke@arm

docs: change Linaro release version to 20.01

We currently use Linaro release software stack version
20.01 in the CI. Reflect that change in the docs.

Signed-off-by: Zelalem Aweke <zelalem.aweke@arm.com>
Change-Id: I0fa9f0163afb0bf399ec503abe9af4f17231f173

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Merge "refactor(plat/marvell/uart): de-duplicate PLAT_MARVELL_UART macros" into integration

Merge "refactor(plat/marvell/uart): remove unused macros" into integration

fix(plat/marvell/armada): select correct pcie reference clock source

when comphy is in pcie mode, correct reference clock need be
selected according to SAR register that reflect the CPx_MPP boot
str

fix(plat/marvell/armada): select correct pcie reference clock source

when comphy is in pcie mode, correct reference clock need be
selected according to SAR register that reflect the CPx_MPP boot
strapping pins. Either from external or from internal

Signed-off-by: Guo Yi <yguo@cavium.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
Change-Id: I99ed64a141e85174cc0f8e9dab5886ab2506efa1

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Merge "fix(morello): initialise CNTFRQ in Non Secure CNTBaseN" into integration

Merge "fix(plat/marvell/a3720/uart): fix configuring UART clock" into integration

refactor(plat/marvell/uart): de-duplicate PLAT_MARVELL_UART macros

Macros PLAT_MARVELL_BOOT_UART* and PLAT_MARVELL_CRASH_UART* are defined
to same values. De-duplicate them into PLAT_MARVELL_UART* m

refactor(plat/marvell/uart): de-duplicate PLAT_MARVELL_UART macros

Macros PLAT_MARVELL_BOOT_UART* and PLAT_MARVELL_CRASH_UART* are defined
to same values. De-duplicate them into PLAT_MARVELL_UART* macros.

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: Iae5daf7cad6a971e6f3dbe561df3d0174106ca7f

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refactor(plat/marvell/uart): remove unused macros

Macros PLAT_MARVELL_BL31_RUN_UART* are not used since commit
d7c4420cb8a7 ("plat/marvell: Migrate to multi-console API").

Remove them.

Signed-off-

refactor(plat/marvell/uart): remove unused macros

Macros PLAT_MARVELL_BL31_RUN_UART* are not used since commit
d7c4420cb8a7 ("plat/marvell: Migrate to multi-console API").

Remove them.

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I5ec959ef4de87dcfb332c017ad2599bf8af6ffc3

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fix(plat/marvell/a3720/uart): fix configuring UART clock

When configuring the UART_BAUD_REG register, the function
console_a3700_core_init() currently only changes the baud divisor field,
leaving ot

fix(plat/marvell/a3720/uart): fix configuring UART clock

When configuring the UART_BAUD_REG register, the function
console_a3700_core_init() currently only changes the baud divisor field,
leaving other fields to their previous value.

This is incorrect, because the baud divisor is computed with the
assumption that the parent clock rate is 25 MHz, and since the other
fields in this register configure the parent clock, which could have
been changed by U-Boot or Linux.

Fix this function to also configure the other fields so that the UART
parent clock is selected to be the xtal clock.

For example without this change TF-A prints only

ERROR: a3700_system_off needs to be implemented

followed by garbage after plat_crash_console_init() is called.

After applying this change instead of garbage it also print crash info:

PANIC at PC : 0x0000000004023800

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I72f338355cc60d939b8bb978d9c7fdd576416b81

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Merge "fix(plat/marvell/a3720/uart): fix UART clock rate value and divisor calculation" into integration

Merge "feat(plat/mdeiatek/mt8195): add display port control in SiP service" into integration

Merge "feat(plat/zynqmp): add support for XCK26 silicon" into integration

fix(morello): initialise CNTFRQ in Non Secure CNTBaseN

Morello exhibits the behavior similar to Juno wherein CNTBaseN.CNTFRQ
can be written but does not reflect the value of the CNTFRQ register
in C

fix(morello): initialise CNTFRQ in Non Secure CNTBaseN

Morello exhibits the behavior similar to Juno wherein CNTBaseN.CNTFRQ
can be written but does not reflect the value of the CNTFRQ register
in CNTCTLBase frame. This doesn't follow ARM ARM in that the value
updated in CNTCTLBase.CNTFRQ is not reflected in CNTBaseN.CNTFRQ.

Hence enable the workaround (applied to Juno) for Morello that updates
the CNTFRQ register in the Non Secure CNTBaseN frame.

Change-Id: Iabe53bf3c25152052107e08321323e4bde5fbef4
Signed-off-by: Manoj Kumar <manoj.kumar3@arm.com>

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feat(plat/mediatek/mpu): add MPU support for DSP

Forbidden domain D4(DSP) access 0x40000000~0x1FFFF0000.

Signed-off-by: Jiaxin Yu <jiaxin.yu@mediatek.com>
Change-Id: If409df10cecbcccc493d7958ab2765

feat(plat/mediatek/mpu): add MPU support for DSP

Forbidden domain D4(DSP) access 0x40000000~0x1FFFF0000.

Signed-off-by: Jiaxin Yu <jiaxin.yu@mediatek.com>
Change-Id: If409df10cecbcccc493d7958ab2765fd110d9009

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Merge "feat(tc0): add support for trusted services" into integration

feat(plat/zynqmp): add support for XCK26 silicon

Add support for XCK26 silicon which is available on SOM board.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Venkatesh Yadav

feat(plat/zynqmp): add support for XCK26 silicon

Add support for XCK26 silicon which is available on SOM board.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Change-Id: Ic98213328702903af8a79f487a2868f3e6d60338

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Merge "fix: rename Matterhorn, Matterhorn ELP, and Klein CPUs" into integration

fix: rename Matterhorn, Matterhorn ELP, and Klein CPUs

This patch renames the Matterhorn, Matterhorn ELP, and Klein CPUs to
Cortex A710, Cortex X2, and Cortex A510 respectively.

Signed-off-by: John

fix: rename Matterhorn, Matterhorn ELP, and Klein CPUs

This patch renames the Matterhorn, Matterhorn ELP, and Klein CPUs to
Cortex A710, Cortex X2, and Cortex A510 respectively.

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I056d3114210db71c2840a24562b51caf2546e195

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