fix(drivers/tzc400): never disable filter 0

Disabling filter 0 causes inability to access DRAM.
An attempt leads to an abort.
ARM manual disallows to disable filter 0, but if we do
that from SRAM, n

fix(drivers/tzc400): never disable filter 0

Disabling filter 0 causes inability to access DRAM.
An attempt leads to an abort.
ARM manual disallows to disable filter 0, but if we do
that from SRAM, nothing bad happens.

This patch prevents disabling of a filter 0, allowing to
reconfigure other filters from DRAM.

Note: this patch doesn't change the logic after reset.
It is only needed in case someone wants to reconfigure the
previously configured TZASC.

Change-Id: I196a0cb110a89afbde97f64a94df3101f28708a4
Signed-off-by: stsp@users.sourceforge.net

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Merge "docs(ff-a): fix specification naming" into integration

Merge "docs(ff-a): managed exit parameter separation" into integration

feat(plat/nxp/common): define default SD buffer

Define default SD buffer address and size in DRAM.

Signed-off-by: Biwen Li <biwen.li@nxp.com>
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-I

feat(plat/nxp/common): define default SD buffer

Define default SD buffer address and size in DRAM.

Signed-off-by: Biwen Li <biwen.li@nxp.com>
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I5872d95b0c1114e05f0e145756e9a6ef39b2fd9a

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feat(driver/nxp/xspi): add MT35XU02G flash info

Add MT35XU02G flash info.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I2dbbdcb454fae4befef

feat(driver/nxp/xspi): add MT35XU02G flash info

Add MT35XU02G flash info.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I2dbbdcb454fae4befef71769f9646c077d72a057

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feat(plat/nxp/common): add SecMon register definition for ch_3_2

Add SecMon register definition for ch_3_2.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.co

feat(plat/nxp/common): add SecMon register definition for ch_3_2

Add SecMon register definition for ch_3_2.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I80d134ea4e94ad234e1a8fbd02798d5fd86d2544

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feat(driver/nxp/dcfg): define RSTCR_RESET_REQ

Define RSTCR_RESET_REQ for Chassis V3.

Signed-off-by: Biwen Li <biwen.li@nxp.com>
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I5cb7019baa

feat(driver/nxp/dcfg): define RSTCR_RESET_REQ

Define RSTCR_RESET_REQ for Chassis V3.

Signed-off-by: Biwen Li <biwen.li@nxp.com>
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I5cb7019baae5fe0d06b3d5e65f185f87ee16ad3a

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feat(plat/nxp/common/psci): define CPUECTLR_TIMER_2TICKS

Define CPUECTLR_TIMER_2TICKS.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: Iecb5ed

feat(plat/nxp/common/psci): define CPUECTLR_TIMER_2TICKS

Define CPUECTLR_TIMER_2TICKS.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: Iecb5ede82939e8502d2f1bc74ec3bfe2a00be65c

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feat(plat/nxp/common): define default PSCI features if not defined

SoC code can define supported features, otherwise use default setting.

Signed-off-by: Biwen Li <biwen.li@nxp.com>
Signed-off-by: J

feat(plat/nxp/common): define default PSCI features if not defined

SoC code can define supported features, otherwise use default setting.

Signed-off-by: Biwen Li <biwen.li@nxp.com>
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I0f11498c1f7558ff0ec2d9b344f3f7a4f5489ced

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feat(plat/nxp/common): define common macro for ARM registers

Define common register macro both for Cortex-A53 and Cortex-A72
because the code will be used by both Cortex platform.

Signed-off-by: Bi

feat(plat/nxp/common): define common macro for ARM registers

Define common register macro both for Cortex-A53 and Cortex-A72
because the code will be used by both Cortex platform.

Signed-off-by: Biwen Li <biwen.li@nxp.com>
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I485661bfe3ed4f214c403ff6af53dc6af1ddf089

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feat(plat/nxp/common): add CCI and EPU address definition

Add CCI and EPU base address definiton for Chassis v3.2.

Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I13250555b6646c1e7ba2e9d

feat(plat/nxp/common): add CCI and EPU address definition

Add CCI and EPU base address definiton for Chassis v3.2.

Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I13250555b6646c1e7ba2e9d7c9efca8501f17b3a

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feat(plat/mediatek/mt8195): add EMI MPU basic drivers

EMI MPU stands for external memory interface memory protect unit.
MT8195 supports 32 regions and 16 domains.
We add basic drivers currently, and

feat(plat/mediatek/mt8195): add EMI MPU basic drivers

EMI MPU stands for external memory interface memory protect unit.
MT8195 supports 32 regions and 16 domains.
We add basic drivers currently, and will add more setting for
EMI MPU in next patch.

Change-Id: Iedc19d8f6fcf1ceb2d8241319b8dc17c885642dd
Signed-off-by: Penny Jan <penny.jan@mediatek.com>

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Merge "fix(plat/synquacer): update scmi power domain off handling" into integration

feat(plat/imx/imx8m/imx8mp): enable Trusted Boot

This patch enables Trusted Boot on the i.MX8MP with BL2 doing image
verification from a FIP prior to hand-over to BL31.

Signed-off-by: Ying-Chun Liu

feat(plat/imx/imx8m/imx8mp): enable Trusted Boot

This patch enables Trusted Boot on the i.MX8MP with BL2 doing image
verification from a FIP prior to hand-over to BL31.

Signed-off-by: Ying-Chun Liu (PaulLiu) <paulliu@debian.org>
Change-Id: Iac1d1d62ea9858f67326a47c1e5ba377f23f9db5

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feat(plat/imx/imx8m/imx8mp): add in BL2 with FIP

Adds bl2 with FIP to the build required for mbed Linux booting where
we do:

BootROM -> SPL -> BL2 -> OPTEE -> u-boot

If NEED_BL2 is specified then

feat(plat/imx/imx8m/imx8mp): add in BL2 with FIP

Adds bl2 with FIP to the build required for mbed Linux booting where
we do:

BootROM -> SPL -> BL2 -> OPTEE -> u-boot

If NEED_BL2 is specified then BL2 will be built and BL31 will have its
address range modified upwards to accommodate. BL31 must be loaded from a
FIP in this case.

If NEED_BL2 is not specified then the current BL31 boot flow is unaffected
and u-boot SPL will load and execute BL31 directly.

Signed-off-by: Ying-Chun Liu (PaulLiu) <paulliu@debian.org>
Change-Id: I78914d6002755f733ea866127cb47982a00f9700

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refactor(plat/imx/imx8m): make image load logic for TBBR FIP booting common

This commit makes the image load logic from imx8mm common for all
imx8m platform.

Signed-off-by: Ying-Chun Liu (PaulLiu)

refactor(plat/imx/imx8m): make image load logic for TBBR FIP booting common

This commit makes the image load logic from imx8mm common for all
imx8m platform.

Signed-off-by: Ying-Chun Liu (PaulLiu) <paulliu@debian.org>
Change-Id: Ibfe2e9cc09d198cb9e309afaf381a0237a4b82ed

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feat(plat/imx/imx8m/imx8mp): add initial definition to facilitate FIP layout

Adds a number of definitions consistent with the established RSB3720
equivalents specifying number of io_handles and bloc

feat(plat/imx/imx8m/imx8mp): add initial definition to facilitate FIP layout

Adds a number of definitions consistent with the established RSB3720
equivalents specifying number of io_handles and block devices.

Signed-off-by: Ying-Chun Liu (PaulLiu) <paulliu@debian.org>
Change-Id: I401e48216d67257137351ee4d0b98904a76fa789

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refactor(plat/imx/imx): make imx io-storage logic for TBBR/FIP common

This commit makes imx image io-storage logic common for all
imx platform.

Signed-off-by: Ying-Chun Liu (PaulLiu) <paulliu@debia

refactor(plat/imx/imx): make imx io-storage logic for TBBR/FIP common

This commit makes imx image io-storage logic common for all
imx platform.

Signed-off-by: Ying-Chun Liu (PaulLiu) <paulliu@debian.org>
Change-Id: I15045ac8f9dfa8cb714e32f9e7475d5eae4e86e4

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feat(plat/imx/imx8m/imx8mp): add imx8mp_private.h to the build

Allows for exporting of FIP related methods cleanly in a private header.

Signed-off-by: Ying-Chun Liu (PaulLiu) <paulliu@debian.org>
C

feat(plat/imx/imx8m/imx8mp): add imx8mp_private.h to the build

Allows for exporting of FIP related methods cleanly in a private header.

Signed-off-by: Ying-Chun Liu (PaulLiu) <paulliu@debian.org>
Change-Id: Iaaad4e69ef89c8a8a74648647d7fd09cd0fdd12a

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fix(plat/synquacer): update scmi power domain off handling

In the SCMI power domain off handling, configure GIC
to prevent interrupt toward to the core to be turned off,
and configure CCN to disable

fix(plat/synquacer): update scmi power domain off handling

In the SCMI power domain off handling, configure GIC
to prevent interrupt toward to the core to be turned off,
and configure CCN to disable coherency when the cluster is turned off.
The same operation is done in SCPI power domain off processing.

This commit adds the missing operation in SCMI power domain
off handling.

Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Change-Id: Ib3523de488500c2e8bdc74e4cb8772a1442d9781

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feat(plat/mediatek/mt8195): add vcore-dvfs support

Add DVFSRC init flow.

Change-Id: Ic5fc78c91359abc12c0f54b01860a7cbe41f3358
Signed-off-by: Dawei Chien <dawei.chien@mediatek.com>

Merge "fix(plat/qti/sc7180): qti smc addition" into integration

feat(plat/rcar3): keep RWDT enabled

In case the WDT is enabled by prior stage, keep it enabled.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: Ie7c0eaf2f59dd8c30a9ef686a70004

feat(plat/rcar3): keep RWDT enabled

In case the WDT is enabled by prior stage, keep it enabled.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: Ie7c0eaf2f59dd8c30a9ef686a7000424f38d6352

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feat(drivers/rcar3): add extra offset if booting B-side

In case MFISBTSTSR bit 4 is 1, that means the loader was started as
B-side. Load the remaining boot components from 8 MiB offset.

Signed-off-

feat(drivers/rcar3): add extra offset if booting B-side

In case MFISBTSTSR bit 4 is 1, that means the loader was started as
B-side. Load the remaining boot components from 8 MiB offset.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: I11d882f30ca4f0cf55fd28d3470ff1063d350d10

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feat(plat/rcar3): modify LifeC register setting for R-Car D3

Modified SECGRP0COND6 and SECGRP1COND6 setting for R-Car D3.

Signed-off-by: Hideyuki Nitta <hideyuki.nitta.jf@hitachi.com>
Signed-off-by

feat(plat/rcar3): modify LifeC register setting for R-Car D3

Modified SECGRP0COND6 and SECGRP1COND6 setting for R-Car D3.

Signed-off-by: Hideyuki Nitta <hideyuki.nitta.jf@hitachi.com>
Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Change-Id: I3f173ac44c11743965c013ef238748b0dc8cabab

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