docs: update supported FVP models as per release 11.15.14

Change-Id: I65da6ead356e3f4ee47c5a6bf391f65309bafcdd
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

docs(maintainers): add Julius Werner as Rockchip platform code owner

The two existing plat/rockchip code owners seem to be no longer active
in the project and are not responding to reviews. There ha

docs(maintainers): add Julius Werner as Rockchip platform code owner

The two existing plat/rockchip code owners seem to be no longer active
in the project and are not responding to reviews. There have been a
couple of small fixup patches[1][2][3] pending for months that couldn't
be checked in for lack of Code-Owner-Review+1 flag. Add myself to the
code owner list to unblock this bottleneck (I have been deeply involved
in the rk3399 port, at least, so I know most of the code reasonably
well).

[1] https://review.trustedfirmware.org/9616
[2] https://review.trustedfirmware.org/9990
[2] https://review.trustedfirmware.org/10415

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Ic7b2bb73c35a9bea91ff46ee445a22819d2045d9

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Merge "refactor(plat/qemu): increase the non-secure DRAM size" into integration

fix(plat/marvell/a3k): Fix building uart-images.tgz.bin archive

For UART secure boot it is required also TIMN image, so pack it into
uart-images.tgz.bin archive which is created by mrvl_uart target.

fix(plat/marvell/a3k): Fix building uart-images.tgz.bin archive

For UART secure boot it is required also TIMN image, so pack it into
uart-images.tgz.bin archive which is created by mrvl_uart target.

$(TIMN_IMAGE) and $(TIM_IMAGE) variables are used only for UART images
so their content needs to be initialized from $(TIMN_UART_CFG) and
$(TIM_UART_CFG) config files. And not from $(TIMN_CFG) and $(TIM_CFG) as
it is now because they are not generated during mrvl_uart target. Fix it
to allow building mrvl_uart target before mrvl_flash target.

To match usage of these variables, rename them to $(TIMN_UART_IMAGE) and
$(TIM_UART_IMAGE).

To not complicate rule for building uart-images.tgz.bin archive, set
list of image files into a new $(UART_IMAGES) variable.

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I83b980abb4047a3afb3ce3026842e1d873c490bf

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refactor(plat/marvell/a3k): Rename *_CFG and *_SIG variables

For TIM config file use TIM name instead of DOIMAGE and use underscores
to make variable names more readable.

Signed-off-by: Pali Rohár

refactor(plat/marvell/a3k): Rename *_CFG and *_SIG variables

For TIM config file use TIM name instead of DOIMAGE and use underscores
to make variable names more readable.

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I1282ce11f1431c15458a143ae7bfcee85eed2432

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feat(plat/rcar3): emit RPC status to DT fragment if RPC unlocked

In case the RCAR_RPC_HYPERFLASH_LOCKED is 0, emit DT node /soc/rpc@ee200000
with property status = "okay" into the DT fragment passed

feat(plat/rcar3): emit RPC status to DT fragment if RPC unlocked

In case the RCAR_RPC_HYPERFLASH_LOCKED is 0, emit DT node /soc/rpc@ee200000
with property status = "okay" into the DT fragment passed to subsequent
software, to indicate the RPC is unlocked.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: Id93c4573ab1c62cf13fa5a803dc5818584a2c13a

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refactor(plat/marvell/a3k): Rename DOIMAGETOOL to TBB

Armada 3700 uses external TBB tool for creating images and does not use
internal TF-A doimage tool from tools/marvell/doimage/

Therefore set co

refactor(plat/marvell/a3k): Rename DOIMAGETOOL to TBB

Armada 3700 uses external TBB tool for creating images and does not use
internal TF-A doimage tool from tools/marvell/doimage/

Therefore set correct name of variable.

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I38a94dca78d483de4c79da597c032e1e5d06d92d

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refactor(plat/marvell/a3k): Remove useless DOIMAGEPATH variable

Armada 3700 uses WTP so use WTP variable directly.

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I216b40ffee1f3f8abba4677f05

refactor(plat/marvell/a3k): Remove useless DOIMAGEPATH variable

Armada 3700 uses WTP so use WTP variable directly.

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I216b40ffee1f3f8abba4677f050ab376c2224ede

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fix(plat/marvell/a3k): Fix check for external dependences

Old Marvell a3700_utils and mv-ddr tarballs do not have to work with
latest TF-A code base. Marvell do not provide these old tarballs on
Ext

fix(plat/marvell/a3k): Fix check for external dependences

Old Marvell a3700_utils and mv-ddr tarballs do not have to work with
latest TF-A code base. Marvell do not provide these old tarballs on
Extranet anymore. Public version on github repository contains all
patches and is working fine, so for public TF-A builds use only public
external dependencies from git.

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: Iee5ac6daa9a1826a5b80a8d54968bdbb8fe72f61

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fix(plat/marvell/a8k): Add missing build dependency for BLE target

BLE source files depend on external Marvell mv-ddr-marvell tree
(specified in $(MV_DDR_PATH) variable) and its header files. Add
de

fix(plat/marvell/a8k): Add missing build dependency for BLE target

BLE source files depend on external Marvell mv-ddr-marvell tree
(specified in $(MV_DDR_PATH) variable) and its header files. Add
dependency on $(MV_DDR_LIB) target which checks that variable
$(MV_DDR_PATH) is correctly set and ensures that make completes
compilation of mv-ddr-marvell tree.

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I73968b24c45d9af1e3500b8db7a24bb4eb2bfa47

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fix(plat/marvell/a8k): Correctly set include directories for individual targets

Do not set all include directories, including those for external targets
in one PLAT_INCLUDES variable.

Instead split

fix(plat/marvell/a8k): Correctly set include directories for individual targets

Do not set all include directories, including those for external targets
in one PLAT_INCLUDES variable.

Instead split them into variables:
* $(PLAT_INCLUDES) for all TF-A BL images
* BLE target specific $(PLAT_INCLUDES) only for Marvell BLE image
* $(MV_DDR_INCLUDES) for targets in external Marvell mv-ddr-marvell tree

Include directory $(CURDIR)/drivers/marvell is required by TF-A BL
images, so move it from ble.mk to a8k_common.mk.

Include directory $(MV_DDR_PATH) is needed only by Marvell BLE image, so
move it into BLE target specific $(PLAT_INCLUDES) variable.

And remaining include directories specified in ble.mk are needed only
for building external dependences from Marvell mv-ddr tree, so move them
into $(MV_DDR_INCLUDES) variable and correctly use it in $(MV_DDR_LIB)
target.

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I331f7de675dca2bc70733d56b768f00d56ae4a67

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fix(plat/marvell/a8k): Require that MV_DDR_PATH is correctly set

Target mrvl_flash depends on external mv_ddr source code which is not
part of TF-A project. Do not expect that it is pre-downloaded a

fix(plat/marvell/a8k): Require that MV_DDR_PATH is correctly set

Target mrvl_flash depends on external mv_ddr source code which is not
part of TF-A project. Do not expect that it is pre-downloaded at some
specific location and require user to specify correct path to mv_ddr
source code via MV_DDR_PATH build option.

TF-A code for Armada 37x0 platform also depends on mv_ddr source code
and already requires passing correct MV_DDR_PATH build option.

So for A8K implement same checks for validity of MV_DDR_PATH option as
are already used by TF-A code for Armada 37x0 platform.

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I792f2bfeab0cec89b1b64e88d7b2c456e22de43a

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feat(plat/rcar3): add a DRAM size setting for M3N

This commit adds a DRAM size setting when building with
RCAR_DRAM_LPDDR4_MEMCONF=2 for M3N Ver.1.1 4GB DRAM.

Signed-off-by: Toshiyuki Ogasahara <to

feat(plat/rcar3): add a DRAM size setting for M3N

This commit adds a DRAM size setting when building with
RCAR_DRAM_LPDDR4_MEMCONF=2 for M3N Ver.1.1 4GB DRAM.

Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Change-Id: Ib7fea862ab2e0bcafaf39ec030384f0fddda9b96

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feat(plat/rcar3): update IPL and Secure Monitor Rev.3.0.0

Update the revision number in the revision management file.

Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-

feat(plat/rcar3): update IPL and Secure Monitor Rev.3.0.0

Update the revision number in the revision management file.

Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Change-Id: I44b9e5a992e8a44cfeafad6d2c1a97aa59baca4e

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feat(plat/rcar3): add new board revision for Salvator-XS/H3ULCB

Add new board revision for 8GB 1rank of Salvator-XS/H3ULCB

Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Si

feat(plat/rcar3): add new board revision for Salvator-XS/H3ULCB

Add new board revision for 8GB 1rank of Salvator-XS/H3ULCB

Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Change-Id: I9e0ef7340d92de9c892fc5bd04abe24ad6ee4286

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feat(drivers/rcar3): ddr: add function to judge a DDR rank

This commit adds the function to change the settings used for DDR
initialization depending on the board ID and DDR rank.

Signed-off-by: To

feat(drivers/rcar3): ddr: add function to judge a DDR rank

This commit adds the function to change the settings used for DDR
initialization depending on the board ID and DDR rank.

Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Change-Id: I94d550cea620748f5b15499fed1b791a69d61592

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fix(drivers/rcar3): ddr: update DDR setting for H3, M3, M3N

[IPL/DDR]
- Update H3, M3, M3N DDR setting rev.0.41.

Signed-off-by: Chiaki Fujii <chiaki.fujii.wj@renesas.com>
Signed-off-by: Yoshifumi H

fix(drivers/rcar3): ddr: update DDR setting for H3, M3, M3N

[IPL/DDR]
- Update H3, M3, M3N DDR setting rev.0.41.

Signed-off-by: Chiaki Fujii <chiaki.fujii.wj@renesas.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Change-Id: Idd2fbea621365d84b566748b5b7d7fb2f0d08168

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fix(drivers/rcar3): i2c_dvfs: fix I2C operation

This commit fixes value to write to the ICCR register according to
the hardware manual.

Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hi

fix(drivers/rcar3): i2c_dvfs: fix I2C operation

This commit fixes value to write to the ICCR register according to
the hardware manual.

Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Change-Id: I1f612a482c012a6739e2f31db80224b222df766c

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fix(drivers/rcar3): fix CPG registers redefinition

This commit deletes the value of the redefined CPG register.

Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by

fix(drivers/rcar3): fix CPG registers redefinition

This commit deletes the value of the redefined CPG register.

Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Change-Id: I05cf4a449ae28adb2ddd59593971a7d0cbcb21de

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fix(drivers/rcar3): emmc: remove CPG_CPGWPR redefinition

emmc_registers.h contains redefinition of
CPG_CPGWPR from bl2_cpg_register.h

Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hita

fix(drivers/rcar3): emmc: remove CPG_CPGWPR redefinition

emmc_registers.h contains redefinition of
CPG_CPGWPR from bl2_cpg_register.h

Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Change-Id: Ie13590100df08f32193653e50191e66ed42d2b28

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fix(plat/rcar3): generate two memory nodes for larger than 2 GiB channel 0

The DRAM channel 0 memory area in 32bit space is limited to 2 GiB window.
Furthermore, the first 128 MiB of this memory win

fix(plat/rcar3): generate two memory nodes for larger than 2 GiB channel 0

The DRAM channel 0 memory area in 32bit space is limited to 2 GiB window.
Furthermore, the first 128 MiB of this memory window are reserved and not
accessible by the system software, hence the 32bit area memory node is
limited to range 0x4800_0000..0xbfff_ffff.

In case there are more than 2 GiB of DRAM populated in channel 0, it is
necessary to generate two memory nodes, once covering the 2 GiB - 128 MiB
area in the 32bit space, and another covering the rest of the memory in
64bit space. This patch implements handling of such a case.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: I3495241fb938e355352e817afaca8f01d04c81d2

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refactor(plat/rcar3): factor out DT memory node generation

Move the code that adds single new memory@ node into the DT fragment passed
to system software into separate function. Adjust the failure m

refactor(plat/rcar3): factor out DT memory node generation

Move the code that adds single new memory@ node into the DT fragment passed
to system software into separate function. Adjust the failure message to be
more specific and print the address range of node which failed to be added.
No functional change.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: Ie42cd7756b045271f070bca93c524fff6238f5a2

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feat(plat/rcar3): add optional support for gzip-compressed BL33

The BL33 size on this platform is limited to 1 MiB, add optional
support for decompressing and starting gzip-compressed BL33, which
ma

feat(plat/rcar3): add optional support for gzip-compressed BL33

The BL33 size on this platform is limited to 1 MiB, add optional
support for decompressing and starting gzip-compressed BL33, which
may help with this size limitation. This functionality is disabled
by default, set RCAR_GEN3_BL33_GZIP=1 during build to enable it.

The BL33 at 0x50000000 should then be gzip compressed, however if
the BL33 does not have a valid gzip header, it is copied to the
correct location and started as-is, this is a fallback for legacy
systems and systems which update to gzip-compressed BL33.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: Id93f1c7e6f17db1ffb952ea086562993473f6efa

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refactor(mpam): remove unused function declaration

Change-Id: Ia660b6554fe4544effd1810e1aca202f95e3c447
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

Merge changes I6f568b85,I78f9c061 into integration

* changes:
fix(plat/xilinx/versal): use sync method for blocking calls
fix(plat/xilinx/zynqmp): use sync method for blocking calls