docs(stm32mp1): fix FIP command with OP-TEE

When building a FIP with OP-TEE as BL32 on STM32MP1, AARCH32_SP=optee
has to be added to the make command.

Change-Id: I900c01957fe4ed7ed13ca955edd91ed1c5

docs(stm32mp1): fix FIP command with OP-TEE

When building a FIP with OP-TEE as BL32 on STM32MP1, AARCH32_SP=optee
has to be added to the make command.

Change-Id: I900c01957fe4ed7ed13ca955edd91ed1c5c5c4fa
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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docs(gcc): update GCC to version 10.3-2021.07

This toolchain provides multiple cross compilers and is publicly
available on developer.arm.com

We build TF-A in CI using:
AArch32 bare-metal target (a

docs(gcc): update GCC to version 10.3-2021.07

This toolchain provides multiple cross compilers and is publicly
available on developer.arm.com

We build TF-A in CI using:
AArch32 bare-metal target (arm-none-eabi)
AArch64 ELF bare-metal target (aarch64-none-elf)

Change-Id: I673e0dce8eb3ca3a004a43158a948431b032e93a
Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>

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Merge "fix(pie): invalidate data cache in the entire image range if PIE is enabled" into integration

Merge "feat(cpu): add support for Hunter CPU" into integration

feat(cpu): add support for Hunter CPU

This patch adds the basic CPU library code to support the Hunter CPU
in TF-A. This CPU is based on the Makalu core so that library code
was adapted as the basis

feat(cpu): add support for Hunter CPU

This patch adds the basic CPU library code to support the Hunter CPU
in TF-A. This CPU is based on the Makalu core so that library code
was adapted as the basis for this patch.

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I956b2dc0f43da7cec3e015252392e2694363e1b3

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Merge "feat(plat/qti/sc7280): add support for pmk7325" into integration

Merge "build(plat/marvell): do not print comments on stdout" into integration

Merge "fix(lib/optee): correct signedness comparison" into integration

fix(pie): invalidate data cache in the entire image range if PIE is enabled

Currently on image entry, the data cache in the RW address range is
invalidated before MMU is enabled to safeguard against

fix(pie): invalidate data cache in the entire image range if PIE is enabled

Currently on image entry, the data cache in the RW address range is
invalidated before MMU is enabled to safeguard against potential
stale data from previous firmware stage. If PIE is enabled however,
RO sections including the GOT may be also modified during pie fixup.
Therefore, to be on the safe side, invalidate the entire image
region if PIE is enabled.

Signed-off-by: Zelalem Aweke <zelalem.aweke@arm.com>
Change-Id: I7ee2a324fe4377b026e32f9ab842617ad4e09d89

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build(plat/marvell): do not print comments on stdout

'#' needs to be before TAB, otherwise comment is printed on stdout during build.

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I502374e

build(plat/marvell): do not print comments on stdout

'#' needs to be before TAB, otherwise comment is printed on stdout during build.

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I502374ef35d91e194dc35b78d31d6884a466fab2

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Merge "fix(cc-713): fix a build failure with CC-713 library" into integration

Merge changes I6daaed9a,I3ef31047 into integration

* changes:
feat(plat/arm): Add DRAM2 to TZC non-secure region
fix(plat/arm): remove unused memory node

fix(scmi): mention "SCMI" in driver initialisation message

Currently the SCMI driver reports:
INFO: Initializing driver on Channel 0
on the console, which is not very specific (which driver?).

A

fix(scmi): mention "SCMI" in driver initialisation message

Currently the SCMI driver reports:
INFO: Initializing driver on Channel 0
on the console, which is not very specific (which driver?).

Add "SCMI" to the message so the user knows what the firmware is trying
to initialise.

Change-Id: Id8202655d07b8e12fe07670d462c6202e6eae2f0
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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Merge "fix(scmi): relax requirement for exact protocol version" into integration

Merge "feat(psci): require validate_power_state to expose CPU_SUSPEND" into integration

Merge "fix(errata_report): correct typo" into integration

Merge "feat(plat/mdeiatek/mt8195): remove adsp event from wakeup source" into integration

Merge changes from topic "ufs_patches" into integration

* changes:
fix(ufs): add reset before DME_LINKSTARTUP
refactor(ufs): add retry logic to ufshc_reset
refactor(ufs): reuse ufshc_send_uic_

Merge changes from topic "ufs_patches" into integration

* changes:
fix(ufs): add reset before DME_LINKSTARTUP
refactor(ufs): add retry logic to ufshc_reset
refactor(ufs): reuse ufshc_send_uic_cmd

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Merge changes I684d54a7,I61339fc5,Ic0dabf3e,Ief09a841 into integration

* changes:
feat(plat/rcar): change process for Suspend To RAM
fix(plat/rcar): change process that copy code to system ram

Merge changes I684d54a7,I61339fc5,Ic0dabf3e,Ief09a841 into integration

* changes:
feat(plat/rcar): change process for Suspend To RAM
fix(plat/rcar): change process that copy code to system ram
fix(plat/rcar): fix cache maintenance process of reading cert header
fix(plat/rcar): fix to load image when option BL2_DCACHE_ENABLE is enabled

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Merge changes Id7d4f5df,If82542cc,I0ba80057,I75a443db,Ifa18b4fc, ... into integration

* changes:
feat(nxp/common/ocram): add driver for OCRAM initialization
feat(plat/nxp/common): add EESR regis

Merge changes Id7d4f5df,If82542cc,I0ba80057,I75a443db,Ifa18b4fc, ... into integration

* changes:
feat(nxp/common/ocram): add driver for OCRAM initialization
feat(plat/nxp/common): add EESR register definition
fix(plat/nxp/ls1028a): fix compile error when enable fuse provision
fix(drivers/nxp/sfp): fix compile warning
fix(plat/nxp/ls1028a): define endianness of scfg and gpio
fix(nxp/scfg): fix endianness checking

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feat(plat/rcar): change process for Suspend To RAM

- Added the function rcar_pwr_domain_pwr_down_wfi() for power down process.
And change the sequence to power down.
- Removed clearing the count o

feat(plat/rcar): change process for Suspend To RAM

- Added the function rcar_pwr_domain_pwr_down_wfi() for power down process.
And change the sequence to power down.
- Removed clearing the count of psci_locks (PSCI exclusive lock) during
Warm Boot.

Signed-off-by: Koichi Yamaguchi <koichi.yamaguchi.zb@hitachi.com>
Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Change-Id: I684d54a798a6dccde15fbebe16c6e104cbb470ed

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fix(plat/rcar): change process that copy code to system ram

Change processing of invalidate instruction cache to after changing
the RAM attribute.

Signed-off-by: Koichi Yamaguchi <koichi.yamaguchi.

fix(plat/rcar): change process that copy code to system ram

Change processing of invalidate instruction cache to after changing
the RAM attribute.

Signed-off-by: Koichi Yamaguchi <koichi.yamaguchi.zb@hitachi.com>
Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> # squash with rcar_gen3: drivers: Disable data cache while Suspend To RAM
Change-Id: I61339fc5415b26074b1e0753da4c4a432e8f83d9

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fix(plat/rcar): fix cache maintenance process of reading cert header

Move calling inv_dcache_range from before io_read to after that.

Signed-off-by: Hideyuki Nitta <hideyuki.nitta.jf@hitachi.com>
S

fix(plat/rcar): fix cache maintenance process of reading cert header

Move calling inv_dcache_range from before io_read to after that.

Signed-off-by: Hideyuki Nitta <hideyuki.nitta.jf@hitachi.com>
Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Change-Id: Ic0dabf3eb94eeeb04099ed5127cdfda79bbac9b3

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fix(plat/rcar): fix to load image when option BL2_DCACHE_ENABLE is enabled

- Modify load destination variable of the Cert Header to static.
- Modify the return value to error (IO_FAIL) when failed t

fix(plat/rcar): fix to load image when option BL2_DCACHE_ENABLE is enabled

- Modify load destination variable of the Cert Header to static.
- Modify the return value to error (IO_FAIL) when failed to check
the Cert Header.

Signed-off-by: Koichi Yamaguchi <koichi.yamaguchi.zb@hitachi.com>
Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Change-Id: Ief09a841ec8d2ae236de82d04855e6a47cfb43f0

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fix(ufs): add reset before DME_LINKSTARTUP

This change aims to make the UFS code more robust by performing a
controller reset if linkstartup fails. This idea was borrowed from
Linux's ufshcd_link_st

fix(ufs): add reset before DME_LINKSTARTUP

This change aims to make the UFS code more robust by performing a
controller reset if linkstartup fails. This idea was borrowed from
Linux's ufshcd_link_startup function.

Signed-off-by: Jorge Troncoso <jatron@google.com>
Change-Id: I6b52148d1bf155b11198dc82a39b1120057adaaf

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