fix(spmd): error macro to use correct print format

Following merge of [1] then [2] broke the build because of an incorrect
format specifier in an ERROR macro. Fix to use the correct print format.

[

fix(spmd): error macro to use correct print format

Following merge of [1] then [2] broke the build because of an incorrect
format specifier in an ERROR macro. Fix to use the correct print format.

[1] https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/5437
[2] https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/9211

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I14d4c31091f6a5f4c3252f6d810e9d2bb2f545c4

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Merge "feat(SPMD): route secure interrupts to SPMC" into integration

Merge changes from topic "st_usb" into integration

* changes:
fix(drivers/usb): add a optional ops get_other_speed_config_desc
fix(drivers/usb): remove unnecessary cast

Merge "fix: libc: use long for 64-bit types on aarch64" into integration

Changing SMC code for transitioning Granule

Changing the SMC code value to conform with RMM for
transitioning a realm granule back to non-secure,
otherwise known as undelegate.

Signed-off-by: Mark

Changing SMC code for transitioning Granule

Changing the SMC code value to conform with RMM for
transitioning a realm granule back to non-secure,
otherwise known as undelegate.

Signed-off-by: Mark Dykes <mark.dykes@arm.com>
Change-Id: Ia45ad6cab538de48c65b071b49e504be234afa2b

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Merge "fix(arm_fpga): Change PL011 UART IRQ" into integration

fix: libc: use long for 64-bit types on aarch64

Use long instead of long long on aarch64 for 64_t stdint types.
Introduce inttypes.h to properly support printf format specifiers for
fixed width type

fix: libc: use long for 64-bit types on aarch64

Use long instead of long long on aarch64 for 64_t stdint types.
Introduce inttypes.h to properly support printf format specifiers for
fixed width types for such change.

Change-Id: I0bca594687a996fde0a9702d7a383055b99f10a1
Signed-off-by: Scott Branden <scott.branden@broadcom.com>

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Merge changes Ic2f90d79,Ieca02425,I615bcc1f,I6a9cb4a2,I5247f8f8, ... into integration

* changes:
fix(errata): workaround for Neoverse V1 erratum 2216392
fix(errata): workaround for Cortex A78 er

Merge changes Ic2f90d79,Ieca02425,I615bcc1f,I6a9cb4a2,I5247f8f8, ... into integration

* changes:
fix(errata): workaround for Neoverse V1 erratum 2216392
fix(errata): workaround for Cortex A78 erratum 2242635
fix(errata): workaround for Neoverse-N2 erratum 2280757
fix(errata): workaround for Neoverse-N2 erratum 2242400
fix(errata): workaround for Neoverse-N2 erratum 2138958
fix(errata): workaround for Neoverse-N2 erratum 2242415

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feat(measured boot): add documentation to build and run PoC

Add documentation to build and run a PoC based on the OP-TEE toolkit
to show how TF-A Measured Boot can interact with a third party (f)TPM

feat(measured boot): add documentation to build and run PoC

Add documentation to build and run a PoC based on the OP-TEE toolkit
to show how TF-A Measured Boot can interact with a third party (f)TPM
service.

Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com>
Change-Id: I11ac99c4ff54ea52aba0731aa7f707d7cd0c4216

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Merge changes from topic "arm_fpga_auto" into integration

* changes:
feat(arm_fpga): write UART baud base clock frequency into DTB
feat(arm_fpga): query PL011 to learn system frequency
refacto

Merge changes from topic "arm_fpga_auto" into integration

* changes:
feat(arm_fpga): write UART baud base clock frequency into DTB
feat(arm_fpga): query PL011 to learn system frequency
refactor(arm_fpga): move command line code into separate function
fix(fdt): avoid output on missing DT property
feat(arm_fpga): add ITS autodetection
feat(arm_fpga): determine GICR base by probing
feat(gicv3): introduce GIC component identification
feat(libfdt): also allow changing base address
fix(arm_fpga): avoid re-linking from executable ELF file

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fix(errata): workaround for Neoverse V1 erratum 2216392

Neoverse V1 erratum 2216392 is a Cat B erratum present in the V1 core.
It applies to revisions r1p0 and r1p1 and is still open. The issue is
a

fix(errata): workaround for Neoverse V1 erratum 2216392

Neoverse V1 erratum 2216392 is a Cat B erratum present in the V1 core.
It applies to revisions r1p0 and r1p1 and is still open. The issue is
also present in r0p0 but there is no workaround in that revision.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN1401781

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: Ic2f90d79c75e8ffef01aac81eddf1bfd8b7164ab

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docs(spm): document s-el0 partition support

This patch adds a brief description of S-EL0 partition support in the
SPMC using ARMv8.1 FEAT_VHE.

Signed-off-by: Raghu Krishnamurthy <raghu.ncstate@gmai

docs(spm): document s-el0 partition support

This patch adds a brief description of S-EL0 partition support in the
SPMC using ARMv8.1 FEAT_VHE.

Signed-off-by: Raghu Krishnamurthy <raghu.ncstate@gmail.com>
Change-Id: Ie079265476604f62d5f2a66684f01341000969d0

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Merge "feat(tc0): add Ivy partition" into integration

fix(errata): workaround for Cortex A78 erratum 2242635

Cortex A78 erratum 2242635 is a Cat B erratum present in the A78 Core.
It applies to revisions r1p0, r1p1, r1p2, and is still open. The issue
i

fix(errata): workaround for Cortex A78 erratum 2242635

Cortex A78 erratum 2242635 is a Cat B erratum present in the A78 Core.
It applies to revisions r1p0, r1p1, r1p2, and is still open. The issue
is also present in r0p0 but there is no workaround for this revision.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN1401784

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: Ieca024254cabbc683ff13a70f3aeb8f2f3c5ce07

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Merge "refactor(stm32mp1): use fconf.mk" into integration

Merge "feat(ff-a): feature retrieval through FFA_FEATURES call" into integration

feat(ff-a): feature retrieval through FFA_FEATURES call

Updated FFA_FEATURES according to FF-A v1.1 in SPMC can also be used
to retrieve feature information, and should now accept other arguments
th

feat(ff-a): feature retrieval through FFA_FEATURES call

Updated FFA_FEATURES according to FF-A v1.1 in SPMC can also be used
to retrieve feature information, and should now accept other arguments
than just FF-A call IDs.

Signed-off-by: J-Alves <joao.alves@arm.com>
Change-Id: I02cc24a31ab3092ec1ce6fed1a9649ffe7136782

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Merge changes from topic "st_usb" into integration

* changes:
fix(drivers/usb): remove deadcode when USBD_EP_NB = 1
fix(drivers/usb): fix Null pointer dereferences in usb_core_set_config

Merge "fix(fdts stm32mp1): correct copyright dates" into integration

refactor(stm32mp1): use fconf.mk

Update STM32MP1 platform.mk file to include fconf.mk.

Change-Id: Idc623a832b4cdf9486835fc612803015f4f1a5f5
Signed-off-by: Yann Gautier <yann.gautier@st.com>

fix(fdts stm32mp1): correct copyright dates

Add 2021 year in the file header Copyright line.

Change-Id: I09f7bef1f746c429ff308286169354e58648a1cd
Signed-off-by: Yann Gautier <yann.gautier@st.com>

fix(sdei): fix assert while kdump issue

Assert condition:
1 Register secure timer(ppi=29) for sdei nmi watchdog;
2 kernel panic and then kdump;
While kdump, kernel mask all cores sdei, secure timer

fix(sdei): fix assert while kdump issue

Assert condition:
1 Register secure timer(ppi=29) for sdei nmi watchdog;
2 kernel panic and then kdump;
While kdump, kernel mask all cores sdei, secure timer trigger
and go to handle_masked_trigger() and assert here:
assert(se->affinity == my_mpidr);

As kernel register with flag=0, mpidr=0 and TF-A set flag to
SDEI_REGF_RM_PE but leave mpidr=0. So set mpidr to fix his
assert issue.

Signed-off-by: Ming Huang <huangming@linux.alibaba.com>
Change-Id: Ia9182f40bde94fb004b46e2a72b186eb0ef05166

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Merge "chore(docs): update supported FVP models doc" into integration

Merge "fix(gpt_rme): add necessary barriers and remove cache clean" into integration

fix(gpt_rme): add necessary barriers and remove cache clean

This patch adds necessary barriers after GPT entries are modified
so that the writes are observed correctly by the GPC hardware.
The share

fix(gpt_rme): add necessary barriers and remove cache clean

This patch adds necessary barriers after GPT entries are modified
so that the writes are observed correctly by the GPC hardware.
The shareability of GPC fetches are changed from OSH to ISH so
that they align with the shareability of MMU attributes for the
region. Thus by adding a dsbishst() between the GPT L1 entry
write as part of granule migration at runtime, we can now remove
the clean cache maintenance operation (CMO) for that region.

Signed-off-by: Soby Mathew <soby.mathew@arm.com>
Signed-off-by: Robert Wakim <robert.wakim@arm.com>
Change-Id: Ib9e405b106f0db95c7fbdb26773c0ed41663a5b4

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