refactor(drivers/marvell/comphy-3700): drop _REG prefixes and suffixes

Some register constants are defined with _REG suffix or REG_ prefix, but
others are not. Unify this by dropping these prefixes

refactor(drivers/marvell/comphy-3700): drop _REG prefixes and suffixes

Some register constants are defined with _REG suffix or REG_ prefix, but
others are not. Unify this by dropping these prefixes / suffixes.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Change-Id: I1ba331c0a4686093ee250bcaf3297349956ac9a8

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refactor(drivers/marvell/comphy-3700): move and add comment for COMPHY_RESERVED_REG

The COMPHY_RESERVED_REG (offset 0x0E) is currently defined between
COMPHY_KVCO_CAL_CTRL (0x02) and COMPHY_DIG_LOOP

refactor(drivers/marvell/comphy-3700): move and add comment for COMPHY_RESERVED_REG

The COMPHY_RESERVED_REG (offset 0x0E) is currently defined between
COMPHY_KVCO_CAL_CTRL (0x02) and COMPHY_DIG_LOOPBACK_EN (0x23).

But this register does not come from PHY lane register space. The
address 0x0E is not relative to PHY lane registers base address.

It only exists in the indirect register space, before PHY lane 2
registers (which start at address 0x200).

Move its definition in the header and add a comment.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Change-Id: Ie726384b980ace83d8ea327df09d928db74c2ab7

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refactor(drivers/marvell/comphy-3700): move Miscellaneous Control 0 register definition

Move the definitions for the Miscellaneous Control 0 register (offset 0x4F),
to leave the registers sorted acc

refactor(drivers/marvell/comphy-3700): move Miscellaneous Control 0 register definition

Move the definitions for the Miscellaneous Control 0 register (offset 0x4F),
to leave the registers sorted according to their offsets.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Change-Id: I9864be5bd00181d21c9334219be4f89c4f032c8b

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refactor(drivers/marvell/comphy-3700): rename PHY_GEN_USB3_5G to PHY_GEN_MAX_USB3_5G

The register name for the value PHY_GEN_USB3_5G is PHY_GEN_MAX. We
already define the mask constant as PHY_GEN_MA

refactor(drivers/marvell/comphy-3700): rename PHY_GEN_USB3_5G to PHY_GEN_MAX_USB3_5G

The register name for the value PHY_GEN_USB3_5G is PHY_GEN_MAX. We
already define the mask constant as PHY_GEN_MAX_MASK. Thus also the
value name should be prefixed with PHY_GEN_MAX_.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Change-Id: Ibf72a66d2e65e240ed2cdbc3a301dbd793e2cb34

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refactor(drivers/marvell/comphy-3700): rename Digital Loopback Enable register constant

The register at offset 0x23 is called Digital Loopback Enable, but the
constant is COMPHY_LOOPBACK_REG0, as if

refactor(drivers/marvell/comphy-3700): rename Digital Loopback Enable register constant

The register at offset 0x23 is called Digital Loopback Enable, but the
constant is COMPHY_LOOPBACK_REG0, as if there were some LOOPBACK_REG1
register or something, which there is not.

Rename the constant to COMPHY_DIG_LOOPBACK_EN.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Change-Id: Ie88bdd864e2c9ab7e8de70ed7f3a13ee8f08ff79

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fix(drivers/marvell/comphy): change reg_set() / reg_set16() to update semantics

Currently reg_set() and reg_set16() are implemented via
mmio_clrsetbits_32(), meaning that first bits from mask are cl

fix(drivers/marvell/comphy): change reg_set() / reg_set16() to update semantics

Currently reg_set() and reg_set16() are implemented via
mmio_clrsetbits_32(), meaning that first bits from mask are cleared,
then data bits are set.

But these function are used everywhere according to update semantics,
where only those bits that are in mask are allowed to be changed.

Example from phy-comphy-cp110.c
mask = HPIPE_RST_CLK_CTRL_PIPE_RST_MASK;
data = 0x1 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET;
/* Set PHY datapath width mode for V0 */
mask |= HPIPE_RST_CLK_CTRL_FIXED_PCLK_MASK;
data |= 0x0 << HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET;
/* Set Data bus width USB mode for V0 */
mask |= HPIPE_RST_CLK_CTRL_PIPE_WIDTH_MASK;
data |= 0x0 << HPIPE_RST_CLK_CTRL_PIPE_WIDTH_OFFSET;
/* Set CORE_CLK output frequency for 250Mhz */
mask |= HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_MASK;
data |= 0x0 << HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_OFFSET;
reg_set(hpipe_addr + HPIPE_RST_CLK_CTRL_REG, data, mask);

Change the implementation to update semantics by anding data with mask.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Change-Id: Ic72a8f64916274e08baef0b3f4c44a4fa07c1a6c

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fix(drivers/marvell/comphy-3700): use reg_set() according to update semantics

Currently reg_set() and reg_set16() are almost everywhere (both in
phy-comphy-3700.c and phy-comphy-cp110.c) used as if

fix(drivers/marvell/comphy-3700): use reg_set() according to update semantics

Currently reg_set() and reg_set16() are almost everywhere (both in
phy-comphy-3700.c and phy-comphy-cp110.c) used as if the semantics were
that of register update function (only bits that are set in mask are
updated):
reg_set(addr, data, mask) {
*addr = (*addr & ~mask) | (data & mask);
}

This comes both from names of arguments (data and mask), and from usage.

But both functions are in fact implemented via mmio_clrsetbits_32(), so
they actually first clear bits from mask and then set bits from data:
reg_set(addr, data, mask) {
*addr = (*addr & ~mask) | data;
}

There are only two places where this is leveraged (where some bits are
put into data argument but they are not put into the mask argument).

Fix those two usages to allow to convert the implementation from
clrsetbits semantics to update semantics.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Change-Id: Ib29a1dd7edcdee7a39c4752dbc9dfcd600d8cb5c

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fix(drivers/marvell/comphy-3700): fix comments about selector register values

The comments about selector register values are wrong.

Bit 0 configures only lane 1, bit 4 only lane 0, and bit 8 lanes

fix(drivers/marvell/comphy-3700): fix comments about selector register values

The comments about selector register values are wrong.

Bit 0 configures only lane 1, bit 4 only lane 0, and bit 8 lanes 0 and
2.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Change-Id: Iffe42374f92654ebe570557e0d462204439cfa31

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fix(drivers/marvell/comphy-3700): fix comment about COMPHY status register

Fix comment about COMPHY status register. PCIe/GbE0 PHY is on lane 1,
while USB3/GbE1 on lane 0.

Signed-off-by: Marek Behú

fix(drivers/marvell/comphy-3700): fix comment about COMPHY status register

Fix comment about COMPHY status register. PCIe/GbE0 PHY is on lane 1,
while USB3/GbE1 on lane 0.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Change-Id: I24734a61727d56f6eab2ed1c366d7a1810dbe19d

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fix(drivers/marvell/comphy-3700): fix reference clock selection value names

The current definitions of reference clock speed register values
#define PCIE_REF_CLOCK_SPEED_25M REF_CLOCK_SPEED_

fix(drivers/marvell/comphy-3700): fix reference clock selection value names

The current definitions of reference clock speed register values
#define PCIE_REF_CLOCK_SPEED_25M REF_CLOCK_SPEED_30M
#define USB3_REF_CLOCK_SPEED_25M REF_CLOCK_SPEED_30M
is ambiguous. The name of the constant implies 25 MHz, but the value
implies 30 MHz, which may make the reader think that the setting has
something to do with both values.

In reality, the values have different tables for SerDes and PCIe/USB3
PHY mode. The value for 25 MHz for PCIe/USB3 mode (0x2) is the value
for 30 MHz for SerDes mode.

Instead of defining the PCIe/USB3 constants relative to SerDes
constants, define them with absolute values, thus making it a little bit
more obvious that different modes have different value tables.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Change-Id: I50c66c6bbe22b9a9bec4685600cb8560524a643c

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fix(drivers/marvell/comphy-3700): drop MODE_REFDIV constant

The MODE_REFDIV constant is only used as mask of the MODE_REFDIV
register, but we already have MODE_REFDIV_MASK constant for that.

Drop M

fix(drivers/marvell/comphy-3700): drop MODE_REFDIV constant

The MODE_REFDIV constant is only used as mask of the MODE_REFDIV
register, but we already have MODE_REFDIV_MASK constant for that.

Drop MODE_REFDIV.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Change-Id: Icabb32189a7ca1a857dcf86cf0846bd0335f75d0

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fix(drivers/marvell/comphy-3700): fix SerDes frequency register value name

Constants SD_SPEED_1_25_G and SD_SPEED_2_5_G refer to SerDes frequency,
which is 1.25x that of data rate, since 1000base-x

fix(drivers/marvell/comphy-3700): fix SerDes frequency register value name

Constants SD_SPEED_1_25_G and SD_SPEED_2_5_G refer to SerDes frequency,
which is 1.25x that of data rate, since 1000base-x and 2500base-x use
the 8b/10b encoding:

mode frequency data rate
1000base-x 1.25 GHz 1 Gbps
2500base-x 3.125 GHz 2.5 Gbps

But the first constant refers to the frequency, while the second to the
data rate, which does not make sense.

Since the values in the specification refer to frequency, change the
name of the constant SD_SPEED_2_5_G to SD_SPEED_3_125_G to also refer to
the frequency, as SD_SPEED_1_25_G does.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Change-Id: I7670b45fa685aff93b3cafd84cf30d93620d8da1

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fix(drivers/marvell/comphy-3700): fix Generation Setting registers names

According to Functional Specification, the common PHY register at offset
0x3f is actually Generation 3 Setting 2, while the r

fix(drivers/marvell/comphy-3700): fix Generation Setting registers names

According to Functional Specification, the common PHY register at offset
0x3f is actually Generation 3 Setting 2, while the register at offset
0x112 is Generation 2 Setting 3.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Change-Id: I4626672cbee2d08da1da7839a3cf3f90e78fa101

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fix(drivers/marvell/comphy-3700): fix PIN_PU_IVREF register name

According to Functional Specification, the register at bit 1 of PHY
Configuration 1 is called PIN_PU_IVREF, not PIN_PU_IVEREF. Fix th

fix(drivers/marvell/comphy-3700): fix PIN_PU_IVREF register name

According to Functional Specification, the register at bit 1 of PHY
Configuration 1 is called PIN_PU_IVREF, not PIN_PU_IVEREF. Fix this.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Change-Id: I912fa4a1956bf0b1b35a24925db03e3dbbe1adf3

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fix(scmi): make msg_header variable volatile

When tf-a is built with the llvm toolchain, the compiler optimizes the
variable in some way which results in SCMI_MSG_GET_TOKEN assert failure
in multipl

fix(scmi): make msg_header variable volatile

When tf-a is built with the llvm toolchain, the compiler optimizes the
variable in some way which results in SCMI_MSG_GET_TOKEN assert failure
in multiple places. This patch makes the msg_header variable in
mailbox_mem struct volatile, which seems to fix the issue.

Signed-off-by: sahil <sahil@arm.com>
Change-Id: I1d28b30a6472fc23ed85adff9cf73dfb536e39cc

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docs(measured-boot): add a platform function for critical data

Added a platform function to measure the critical data and record its
measurement.
Also, corrected a return value of 'plat_mboot_measur

docs(measured-boot): add a platform function for critical data

Added a platform function to measure the critical data and record its
measurement.
Also, corrected a return value of 'plat_mboot_measure_image' function
in the documentation.

Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: I576676f654e517c2010ca1d5a87a1f7277d581c3

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feat(fvp): measure critical data

Implemented a platform function 'plat_mboot_measure_critical_data' to
measure critical data and record its measurement using the Event Log
driver.
'bl2_plat_mboot_fi

feat(fvp): measure critical data

Implemented a platform function 'plat_mboot_measure_critical_data' to
measure critical data and record its measurement using the Event Log
driver.
'bl2_plat_mboot_finish' function invokes this platform function
immediately after populating the critical data.

Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: Ia198295c6e07ab26d436eab1ff90df2cf28303af

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fix(fiptool): respect OPENSSL_DIR

fiptool links to libcrypto, so as with the other tools it should respect
OPENSSL_DIR for include/library paths.

Change-Id: Icd8c15fa5097db1da9a3a9222d9e267548c4c7e

fix(fiptool): respect OPENSSL_DIR

fiptool links to libcrypto, so as with the other tools it should respect
OPENSSL_DIR for include/library paths.

Change-Id: Icd8c15fa5097db1da9a3a9222d9e267548c4c7e2
Signed-off-by: Ross Burton <ross.burton@arm.com>

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refactor(measured-boot): add generic macros for using Crypto library

It doesn't look correct to use mbed TLS defines directly in the Event
Log driver as this driver may use another Crypto library in

refactor(measured-boot): add generic macros for using Crypto library

It doesn't look correct to use mbed TLS defines directly in the Event
Log driver as this driver may use another Crypto library in future.
Hence mbed TLS Crypto dependency on Event Log driver is removed by
introducing generic Crypto defines and uses those in the Event Log
driver to call Crypto functions.
Also, updated mbed TLS glue layer to map these generic Crypto defines
to mbed TLS library defines.

Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: Ibc9c751f60cbce4d3f3cf049b7c53b3d05cc6735

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fix(rmmd): align RMI and GTSI FIDs with SMCCC

This patch allocates the RMI and GTSI FIDs from the reserved
range in Standard Secure Service call range of SMCCC.

Signed-off-by: Subhasish Ghosh <subh

fix(rmmd): align RMI and GTSI FIDs with SMCCC

This patch allocates the RMI and GTSI FIDs from the reserved
range in Standard Secure Service call range of SMCCC.

Signed-off-by: Subhasish Ghosh <subhasish.ghosh@arm.com>
Change-Id: I82e77778882194c2a78ca6340788d53bab7c3a50

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Merge "refactor(measured boot): rename a macro INVALID_ID to EVLOG_INVALID_ID" into integration

Merge "fix(docs): update the v2.6 change-log" into integration

fix(docs): update the v2.6 change-log

Updated the v2.6 change-log for below:
1. Moved ETE/ETM related changes under separate scope
2. Added manually commit log for Demeter CPU

Change-Id: Ib5b5f994f

fix(docs): update the v2.6 change-log

Updated the v2.6 change-log for below:
1. Moved ETE/ETM related changes under separate scope
2. Added manually commit log for Demeter CPU

Change-Id: Ib5b5f994f603af6c82b1400256752581a7931268
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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refactor(plat/synquacer): update PSCI system_off handling

SynQuacer SoC contains a Cortex-M3 System Control Processor(SCP)
which manages system power.
This commit modifies the PSCI system_off handli

refactor(plat/synquacer): update PSCI system_off handling

SynQuacer SoC contains a Cortex-M3 System Control Processor(SCP)
which manages system power.
This commit modifies the PSCI system_off handling to call SCMI,
same as other PSCI calls. System power-off is done by turing off
the ATX power supply through GPIO, this operation is transferred
to SCP.

Note that this commit modifies only the SCMI case, obsolete SCPI
implementation is not updated.

Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Change-Id: I6c1009e67cccd1eb5d14c338c3df9103d63709dd

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fix(plat/socionext/synquacer): initialise CNTFRQ in Non Secure CNTBaseN

The GTimer implemented on SynQuacer has similar issue found on Juno
wherein CNTBaseN.CNTFRQ can be written but does not reflec

fix(plat/socionext/synquacer): initialise CNTFRQ in Non Secure CNTBaseN

The GTimer implemented on SynQuacer has similar issue found on Juno
wherein CNTBaseN.CNTFRQ can be written but does not reflect the value
of the CNTFRQ register in CNTCTLBase frame. This doesn't follow ARM ARM
in that the value updated in CNTCTLBase.CNTFRQ is not reflected
in CNTBaseN.CNTFRQ.

Hence enable the workaround (applied to Juno) for SynQuacer that updates
the CNTFRQ register in the Non Secure CNTBaseN frame.

Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Change-Id: I5204fb57f28c0945812814f008c4905ef0882e2b

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