feat(plat/rcar3): modify type for Internal function argument

Modify the type of the variable that stores the value for MPIDR
in the internal function from uint64_t to u_register_t.

Signed-off-by: K

feat(plat/rcar3): modify type for Internal function argument

Modify the type of the variable that stores the value for MPIDR
in the internal function from uint64_t to u_register_t.

Signed-off-by: Koichi Yamaguchi <koichi.yamaguchi.zb@hitachi.com>
Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: Ib5bda93d5432e0412132bddf41ead8ee3fcf9e46

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feat(plat/rcar3): modify sequence for update value for WUPMSKCA57/53

Add new function so that the value of bit at WUPMSKCA57/53,
which points to CPU other than the BOOT CPU, is 1 at initialization.

feat(plat/rcar3): modify sequence for update value for WUPMSKCA57/53

Add new function so that the value of bit at WUPMSKCA57/53,
which points to CPU other than the BOOT CPU, is 1 at initialization.
Modify sequence so that value of each bit for CPU at WUPMSKCA57/53 is
basically 0 and target bit value is changed to 1 only when CPU_OFF.

Signed-off-by: Koichi Yamaguchi <koichi.yamaguchi.zb@hitachi.com>
Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: Id5dafc04e1dbaf265c8b67b903c335bb1af49914

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fix(plat/rcar3): fix to bit operation for WUPMSKCA57/53

Change internal function to call when updating value for WUPMSKCA57/53.

Signed-off-by: Koichi Yamaguchi <koichi.yamaguchi.zb@hitachi.com>
Sig

fix(plat/rcar3): fix to bit operation for WUPMSKCA57/53

Change internal function to call when updating value for WUPMSKCA57/53.

Signed-off-by: Koichi Yamaguchi <koichi.yamaguchi.zb@hitachi.com>
Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: Id20e65e27861dd73a149ff487123859581a9b5c5

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Merge "feat(plat/zynqmp): disable the -mbranch-protection flag" into integration

Merge changes from topic "a3700-comphy-fixes-1" into integration

* changes:
refactor(drivers/marvell/comphy-3700): rename Clock Source Low value constants
refactor(drivers/marvell/comphy-3700):

Merge changes from topic "a3700-comphy-fixes-1" into integration

* changes:
refactor(drivers/marvell/comphy-3700): rename Clock Source Low value constants
refactor(drivers/marvell/comphy-3700): rename Clock Source Low register constants
refactor(drivers/marvell/comphy-3700): rename Reset and Clock Control register constants
refactor(drivers/marvell/comphy-3700): rename Lane Status 1 register constants
refactor(drivers/marvell/comphy-3700): rename Miscellaneous Control register constants
refactor(drivers/marvell/comphy-3700): rename Idle Sync Enable register constants
refactor(drivers/marvell/comphy-3700): unify Generation Settings register values
refactor(drivers/marvell/comphy-3700): unify Generation Settings register names
refactor(drivers/marvell/comphy-3700): drop _ADDR suffixes
refactor(drivers/marvell/comphy-3700): drop _REG prefixes and suffixes
refactor(drivers/marvell/comphy-3700): move and add comment for COMPHY_RESERVED_REG
refactor(drivers/marvell/comphy-3700): move Miscellaneous Control 0 register definition
refactor(drivers/marvell/comphy-3700): rename PHY_GEN_USB3_5G to PHY_GEN_MAX_USB3_5G
refactor(drivers/marvell/comphy-3700): rename Digital Loopback Enable register constant
fix(drivers/marvell/comphy): change reg_set() / reg_set16() to update semantics
fix(drivers/marvell/comphy-3700): use reg_set() according to update semantics
fix(drivers/marvell/comphy-3700): fix comments about selector register values
fix(drivers/marvell/comphy-3700): fix comment about COMPHY status register
fix(drivers/marvell/comphy-3700): fix reference clock selection value names
fix(drivers/marvell/comphy-3700): drop MODE_REFDIV constant
fix(drivers/marvell/comphy-3700): fix SerDes frequency register value name
fix(drivers/marvell/comphy-3700): fix Generation Setting registers names
fix(drivers/marvell/comphy-3700): fix PIN_PU_IVREF register name

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Merge changes from topic "mb_critical_data" into integration

* changes:
docs(measured-boot): add a platform function for critical data
feat(fvp): measure critical data

Merge "feat(stm32mp1): preserve the PLL4 settings for USB boot" into integration

docs(build-options): add build macros for features FGT,AMUv1 and ECV

This patch adds macros explicit to the features - FEAT_FGT,FEAT_AMUv1
and FEAT_ECV respectively. It assists in controlled access

docs(build-options): add build macros for features FGT,AMUv1 and ECV

This patch adds macros explicit to the features - FEAT_FGT,FEAT_AMUv1
and FEAT_ECV respectively. It assists in controlled access to the set
of registers (HDFGRTR_EL2, HAFGRTR_EL2 and CNTPOFF_EL2) under the
influence of these features during context save and restore routines.

Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
Change-Id: I5082ea6687a686d8c5af3fe8bf769957cf3078b0

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fix(amu): fault handling on EL2 context switch

The HAFGRTR_EL2 register is UNDEFINED unless the CPU supports both
FEAT_FGT and FEAT_AMUv1. FEAT_FGT is mandatory for v8.6-A and upwards,
but FEAT_AMUv

fix(amu): fault handling on EL2 context switch

The HAFGRTR_EL2 register is UNDEFINED unless the CPU supports both
FEAT_FGT and FEAT_AMUv1. FEAT_FGT is mandatory for v8.6-A and upwards,
but FEAT_AMUv1 is optional (from v8.4-A upwards), and as such any
8.6-A cores today without support for FEAT_AMUv1 will trigger an
undefined instruction exception on accessing this register.

Currently ARM_ARCH_AT_LEAST macro has been used to associate with an
architecture extension allowing to access HAFGRTR_EL2 register. This
condition should be replaced with macros specific to individual
features. This patch adds a new set of macros "ENABLE_FEAT_FGT,
ENABLE_FEAT_AMUv1, ENABLE_FEAT_ECV" under build options to provide
controlled access to the HAFGRTR_EL2 register.

Further to ensure that the the build options passed comply
with the given hardware implementation, a feature detection mechanism,
checking whether build options match with the architecture is required
at bootime. This will be implemented and pushed later in a separate
patch.

Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
Change-Id: Ie390f4babe233b8b09455290277edbddecd33ead

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Merge "fix(rmmd/sve): enable/disable SVE/FPU for Realms" into integration

feat(plat/zynqmp): disable the -mbranch-protection flag

With new gcc11.2 by default the -mbranch-protection is
set to "standard" which is leading to increase the text
section by 4Kb. As the ZynqMP u

feat(plat/zynqmp): disable the -mbranch-protection flag

With new gcc11.2 by default the -mbranch-protection is
set to "standard" which is leading to increase the text
section by 4Kb. As the ZynqMP uses the ARMv8 architecture,
so there is no impact when we disable the branch protection.
These instructions do not provide the branch protection in
architectures before Armv8.3-A.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Change-Id: I36f7a55abf99f50df2ee265255598d83b1f480c6

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Merge "fix(rmmd): align RMI and GTSI FIDs with SMCCC" into integration

Merge "refactor(measured-boot): add generic macros for using Crypto library" into integration

fix(rmmd/sve): enable/disable SVE/FPU for Realms

This patch enable/disable SVE/FPU for Realms depending
upon it's state in NS.

When this feature is enabled, traps to EL3 on SVE/FPU access from
Real

fix(rmmd/sve): enable/disable SVE/FPU for Realms

This patch enable/disable SVE/FPU for Realms depending
upon it's state in NS.

When this feature is enabled, traps to EL3 on SVE/FPU access from
Realms are disabled. However, RMM must ensure that the Realm <-> NS
SVE/FPU registers are not corrupted by each other and Realms do
not leak information to NS.

Change-Id: I0a27a055787976507017b72879ba6458f066624e
Signed-off-by: Subhasish Ghosh <subhasish.ghosh@arm.com>

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Merge "fix(plat/socionext/synquacer): initialise CNTFRQ in Non Secure CNTBaseN" into integration

Merge "refactor(plat/synquacer): update PSCI system_off handling" into integration

refactor(drivers/marvell/comphy-3700): rename Clock Source Low value constants

The constants BUNDLE_PERIOD_SCALE and PLL_READY_DLY refer to two
multi-bit registers within the Clock Source Low regist

refactor(drivers/marvell/comphy-3700): rename Clock Source Low value constants

The constants BUNDLE_PERIOD_SCALE and PLL_READY_DLY refer to two
multi-bit registers within the Clock Source Low register. These
constants are used as masks for those registers (and values are not
defined since we are writing zeros to them).

Give them the _MASK suffix.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Change-Id: Id469d0ab4c755d2d6a0150a1ade33dd9d0293667

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refactor(drivers/marvell/comphy-3700): rename Clock Source Low register constants

The register at offset 0x1C3 is called Clock Source Low in functional
specification, but we use constant name GLOB_C

refactor(drivers/marvell/comphy-3700): rename Clock Source Low register constants

The register at offset 0x1C3 is called Clock Source Low in functional
specification, but we use constant name GLOB_CLK_SRC_LO. Rename it to
RST_CLK_CTRL instead.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Change-Id: If7ca460cb166f3828678e1e09c4e6caf5bb77770

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refactor(drivers/marvell/comphy-3700): rename Reset and Clock Control register constants

The register at offset 0x1C1 is called Reset and Clock Control in
functional specification, but we use consta

refactor(drivers/marvell/comphy-3700): rename Reset and Clock Control register constants

The register at offset 0x1C1 is called Reset and Clock Control in
functional specification, but we use constant name GLOB_PHY_CTRL0.
Rename it to RST_CLK_CTRL instead.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Change-Id: I5dac8913bd0686d4f5bd74b91cb7d07ba06df72b

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refactor(drivers/marvell/comphy-3700): rename Lane Status 1 register constants

Rename the Lane Status 1 register constants from LANE_STATUS1 to
LANE_STAT1, to use an abbreviation similar to that for

refactor(drivers/marvell/comphy-3700): rename Lane Status 1 register constants

Rename the Lane Status 1 register constants from LANE_STATUS1 to
LANE_STAT1, to use an abbreviation similar to that for Lane
Configuration registers (where we use LANE_CFGx instead of LANE_CONFIGx
or LANE_CONFIGURATIONx).

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Change-Id: Ie329d5a93615efe261802a2f027475b602a5c840

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refactor(drivers/marvell/comphy-3700): rename Miscellaneous Control register constants

Rename the Miscellaneous Control register constants from MISC_REGx to
MISC_CTRLx.

Signed-off-by: Marek Behún <

refactor(drivers/marvell/comphy-3700): rename Miscellaneous Control register constants

Rename the Miscellaneous Control register constants from MISC_REGx to
MISC_CTRLx.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Change-Id: I4d43bbda44b090de4ecf2d52cfc468f9683cc3b5

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refactor(drivers/marvell/comphy-3700): rename Idle Sync Enable register constants

According to the functional specification, the register at offset 0x48
is called Idle Sync Enable, not Unit Control

refactor(drivers/marvell/comphy-3700): rename Idle Sync Enable register constants

According to the functional specification, the register at offset 0x48
is called Idle Sync Enable, not Unit Control or some such.

Rename the constants.

Only bit 12 of this register is defined, all other bits are reserved.
But for some reason the code needs the default value of the other bits,
so we also rename constant UNIT_CTRL_DEFAULT_VALUE to
IDLE_SYNC_EN_DEFAULT_VALUE.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Change-Id: Ia4f80f945a8f31c190cd9a1875d50d892e72825f

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refactor(drivers/marvell/comphy-3700): unify Generation Settings register values

Generation Settings registers have the same layout for different
generations and same setting (i.e. Generation 2 Sett

refactor(drivers/marvell/comphy-3700): unify Generation Settings register values

Generation Settings registers have the same layout for different
generations and same setting (i.e. Generation 2 Settings 2 register has
the same layout as Generation 3 Settings 2).

So it does not make sense to prefix the constants for Settings 2 with
G3.

Instead change the prefixes to GSx_ for settings register x.

For Settings 2 of Gen 2 and Gen 3 we have some definitions in the first
and some in the second. Move them all to the first defined register (in
this case Gen 2, since the constant for Gen 1 is not defined because it
is not used).

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Change-Id: I15c337eb58aa37fd99fe388fd59373aa325a3a92

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refactor(drivers/marvell/comphy-3700): unify Generation Settings register names

Sometimes we call the constants GENx_SET_y, sometimes GENx_SETTINGS_y,
and sometimes GENx_SETTING_y.

Unify this into

refactor(drivers/marvell/comphy-3700): unify Generation Settings register names

Sometimes we call the constants GENx_SET_y, sometimes GENx_SETTINGS_y,
and sometimes GENx_SETTING_y.

Unify this into GENx_SETy.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Change-Id: I3810fb52b2897fe6730ef6e58d434c47cfef14a9

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refactor(drivers/marvell/comphy-3700): drop _ADDR suffixes

COMPHY register addresses are defined twice
- once for indirect access, where the constants are of the form
COMPHY_<register_name>
- once

refactor(drivers/marvell/comphy-3700): drop _ADDR suffixes

COMPHY register addresses are defined twice
- once for indirect access, where the constants are of the form
COMPHY_<register_name>
- once for direct access, with constants of the form
<register_name>_ADDR

But sometimes the first case also has this _ADDR suffix (and other times
not).

Drop it from those places to unify how we define these registers.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Change-Id: Ibf95be8ade231d0e42258f40614a5f0974d280bd

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