| a6a0af57 | 06-Oct-2021 |
Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> |
feat(plat/mediatek/mt8186): initialize systimer
Add systimer to support timer function.
TEST=build pass
BUG=b:202871018
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I505f7d0944
feat(plat/mediatek/mt8186): initialize systimer
Add systimer to support timer function.
TEST=build pass
BUG=b:202871018
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I505f7d094410d178e4203e3a9294b851a30ba150
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| 1b17e34c | 03-Oct-2021 |
Penny Jan <penny.jan@mediatek.corp-partner.google.com> |
feat(plat/mediatek/mt8186): add EMI MPU basic driver
EMI MPU stands for external memory interface memory protect unit.
MT8186 supports 32 regions and 16 domains.
We add basic driver currently, and w
feat(plat/mediatek/mt8186): add EMI MPU basic driver
EMI MPU stands for external memory interface memory protect unit.
MT8186 supports 32 regions and 16 domains.
We add basic driver currently, and will add more settings for
EMI MPU in next patch.
TEST=build pass
BUG=b:202871018
Signed-off-by: Penny Jan <penny.jan@mediatek.corp-partner.google.com>
Change-Id: Ia9e5030164e40e060a05e8f91d2ac88258c2e98e
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| 47833abd | 22-Dec-2021 |
Bipin Ravi <bipin.ravi@arm.com> |
Merge "fix(errata): workaround for Cortex X2 erratum 2002765" into integration |
| c2d75fa7 | 22-Dec-2021 |
Bipin Ravi <bipin.ravi@arm.com> |
Merge "fix(errata): workaround for Cortex X2 erratum 2083908" into integration |
| c8076a0e | 21-Dec-2021 |
Mark Dykes <mark.dykes@arm.com> |
Merge "fix(doc): update TF-A v2.7 release date in the release information page" into integration |
| e16045de | 03-Dec-2021 |
johpow01 <john.powell@arm.com> |
fix(errata): workaround for Cortex X2 erratum 2058056
Cortex X2 erratum 2058056 is a Cat B erratum present in the X2 core.
It applies to revisions r0p0, r1p0, and r2p0 and is still open.
There are
fix(errata): workaround for Cortex X2 erratum 2058056
Cortex X2 erratum 2058056 is a Cat B erratum present in the X2 core.
It applies to revisions r0p0, r1p0, and r2p0 and is still open.
There are 2 ways this workaround can be accomplished, the first of
which involves executing a few additional instructions around MSR
writes to CPUECTLR when disabling the prefetcher. (see SDEN for
details)
However, this patch implements the 2nd possible workaround which sets
the prefetcher into its most conservative mode, since this workaround
is generic.
SDEN can be found here:
https://developer.arm.com/documentation/SDEN1775100
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: Idb20d9928c986616cd5bedf40bb29d46d384cfd3
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| 3e80e840 | 21-Dec-2021 |
Bipin Ravi <bipin.ravi@arm.com> |
fix(doc): update TF-A v2.7 release date in the release information page
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: Iae84f82518ab89edc204a23083d5f4168449c2bf |
| ab556c9c | 18-Dec-2021 |
Manish V Badarkhe <Manish.Badarkhe@arm.com> |
fix(fiptool): avoid packing the zero size images in the FIP
Updated the fiptool to avoid packing the zero size images in
the FIP.
Also, updated the commitlint-json file to cover the fiptool
changes
fix(fiptool): avoid packing the zero size images in the FIP
Updated the fiptool to avoid packing the zero size images in
the FIP.
Also, updated the commitlint-json file to cover the fiptool
changes under a separate scope.
Change-Id: Id7ac3dcff0c7318546e49308d0f17b6cbd5eb24b
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
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| f480c9c4 | 17-Dec-2021 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "fix(stm32mp1): correct include order" into integration |
| 34ee76db | 02-Dec-2021 |
johpow01 <john.powell@arm.com> |
fix(errata): workaround for Cortex X2 erratum 2002765
Cortex X2 erratum 2002765 is a Cat B erratum present in the X2 core.
It applies to revisions r0p0, r1p0, and r2p0 and is still open.
SDEN can b
fix(errata): workaround for Cortex X2 erratum 2002765
Cortex X2 erratum 2002765 is a Cat B erratum present in the X2 core.
It applies to revisions r0p0, r1p0, and r2p0 and is still open.
SDEN can be found here:
https://developer.arm.com/documentation/SDEN1775100
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I11576a03bfd8a6b1bd9ffef4430a097d763ca3cf
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| 1d996e56 | 17-Dec-2021 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge changes from topic "morello_plat_support" into integration
* changes:
feat(morello): expose scmi protocols in fdts
fix(morello): change the AP runtime UART address
feat(morello): add sup
Merge changes from topic "morello_plat_support" into integration
* changes:
feat(morello): expose scmi protocols in fdts
fix(morello): change the AP runtime UART address
feat(morello): add support for nt_fw_config
feat(morello): split platform_info sds struct
feat(morello): add changes to enable TBBR boot
feat(morello): add DTS for Morello SoC platform
feat(morello): configure DMC-Bing mode
feat(morello): zero out the DDR memory space
feat(morello): add TARGET_PLATFORM flag
fix(morello): fix SoC reference clock frequency
fix(arm): use PLAT instead of TARGET_PLATFORM
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| ff7675eb | 17-Dec-2021 |
Yann Gautier <yann.gautier@st.com> |
fix(stm32mp1): correct include order
Warnings about header files include order were triggered by CI.
Correct the include order to mathc CI requirements.
Change-Id: Iaca959add924e0e1fa2e56fab2348f0e
fix(stm32mp1): correct include order
Warnings about header files include order were triggered by CI.
Correct the include order to mathc CI requirements.
Change-Id: Iaca959add924e0e1fa2e56fab2348f0ee36e5fa7
Signed-off-by: Yann Gautier <yann.gautier@st.com>
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| 1db6cd60 | 01-Dec-2021 |
johpow01 <john.powell@arm.com> |
fix(errata): workaround for Cortex X2 erratum 2083908
Cortex X2 erratum 2083908 is a Cat B erratum present in the Cortex
X2 core. It applies to revision r2p0 and is still open.
SDEN can be found he
fix(errata): workaround for Cortex X2 erratum 2083908
Cortex X2 erratum 2083908 is a Cat B erratum present in the Cortex
X2 core. It applies to revision r2p0 and is still open.
SDEN can be found here:
https://developer.arm.com/documentation/SDEN1775100
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: Id9dca2b042bf48e75fb3013ab37d1c5925824728
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| e6b1a9ab | 16-Dec-2021 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "feat(plat/fvp_r): Threat Model for TF-A v8-R64 Support" into integration |
| 65c2d2a8 | 16-Dec-2021 |
Olivier Deprez <olivier.deprez@arm.com> |
Merge "fix(amu): add default value for ENABLE_FEAT_FGT and ENABLE_FEAT_ECV flags" into integration |
| 87639aab | 03-Dec-2021 |
Anurag Koul <anurag.koul@arm.com> |
feat(morello): expose scmi protocols in fdts
Add 'firmware' node in morello-soc.dts to expose SCMI
support to the kernel. The SCMI protocols supported at
the moment are SCMI Base, Clock and Perf (DV
feat(morello): expose scmi protocols in fdts
Add 'firmware' node in morello-soc.dts to expose SCMI
support to the kernel. The SCMI protocols supported at
the moment are SCMI Base, Clock and Perf (DVFS).
The current mailbox memory region in MHU SRAM has an issue
with any access not aligned to a 4-byte boundary. So, the SCMI
mailbox memory region has been relocated to AP non-trusted
RAM to get around the problem.
Signed-off-by: Anurag Koul <anurag.koul@arm.com>
Change-Id: Ibcbce8823b751a0fc3be7e9bc3588c1dc47ae024
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| 07302a23 | 02-Dec-2021 |
Chandni Cherukuri <chandni.cherukuri@arm.com> |
fix(morello): change the AP runtime UART address
SoC UART1 is internally connected to MCP UART1 so this
cannot be used as AP runtime UART instead we use the
IOFPGA UART0 as the AP runtime UART.
Sig
fix(morello): change the AP runtime UART address
SoC UART1 is internally connected to MCP UART1 so this
cannot be used as AP runtime UART instead we use the
IOFPGA UART0 as the AP runtime UART.
Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
Change-Id: Iecefb0d2cb875b3ecf97e0983b06f6e914835021
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| 6ad6465e | 18-Nov-2021 |
sah01 <sahil@arm.com> |
feat(morello): add support for nt_fw_config
This patch adds support to load nt_fw_config
with the information from plat_info sds
structure which is then passed from BL2 to BL33.
Signed-off-by: sah0
feat(morello): add support for nt_fw_config
This patch adds support to load nt_fw_config
with the information from plat_info sds
structure which is then passed from BL2 to BL33.
Signed-off-by: sah01 <sahil@arm.com>
Change-Id: I2242da7404c72a4f9c2e3d7f3b5c154890a78526
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| 4a7a9daf | 02-Dec-2021 |
sah01 <sahil@arm.com> |
feat(morello): split platform_info sds struct
Different platform_info sds struct definition will be used
for fvp and soc.
Signed-off-by: sahil <sahil@arm.com>
Change-Id: I92f0e1b2d0d755ad0405ceebfe
feat(morello): split platform_info sds struct
Different platform_info sds struct definition will be used
for fvp and soc.
Signed-off-by: sahil <sahil@arm.com>
Change-Id: I92f0e1b2d0d755ad0405ceebfeb78d6e4c67013d
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| 4af53977 | 10-Jan-2021 |
Manoj Kumar <manoj.kumar3@arm.com> |
feat(morello): add changes to enable TBBR boot
This patch adds all SOC and FVP related changes required to boot
a standard TBBR style boot on Morello.
Signed-off-by: sahil <sahil@arm.com>
Change-Id
feat(morello): add changes to enable TBBR boot
This patch adds all SOC and FVP related changes required to boot
a standard TBBR style boot on Morello.
Signed-off-by: sahil <sahil@arm.com>
Change-Id: Ib8f7f326790b13082cbe8db21a980e048e3db88c
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|
| e119c205 | 16-Dec-2021 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "docs(ff-a): boot order field of SPs manifest" into integration |
| dc669220 | 10-Nov-2021 |
Gary Morrison <gary.morrison@arm.com> |
feat(plat/fvp_r): Threat Model for TF-A v8-R64 Support
Threat model for the current, BL1-only R-class support.
Signed-off-by: Gary Morrison <gary.morrison@arm.com>
Change-Id: I8479d5cb30f3cf391928
feat(plat/fvp_r): Threat Model for TF-A v8-R64 Support
Threat model for the current, BL1-only R-class support.
Signed-off-by: Gary Morrison <gary.morrison@arm.com>
Change-Id: I8479d5cb30f3cf3919281cc8dc1f21cada9511e0
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| 820371b1 | 15-Dec-2021 |
Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com> |
fix(amu): add default value for ENABLE_FEAT_FGT and ENABLE_FEAT_ECV flags
ENABLE_FEAT_FGT and ENABLE_FEAT_ECV macros are used to access
HDFGRTR_EL2 and CNTPOFF_EL2 registers respectively. These flag
fix(amu): add default value for ENABLE_FEAT_FGT and ENABLE_FEAT_ECV flags
ENABLE_FEAT_FGT and ENABLE_FEAT_ECV macros are used to access
HDFGRTR_EL2 and CNTPOFF_EL2 registers respectively. These flags are set
to true for v8.6 and upwards and are not handled explicitly for lower
architecture versions.
This patch adds definitive default value to these build macros, so that
for v8.5 and below, they are not overridden and set to true by the gcc.
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
Change-Id: Ic300194c8ad77558be9a0e00153e42185bf2c58c
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| c1ff1791 | 14-Dec-2021 |
J-Alves <joao.alves@arm.com> |
docs(ff-a): boot order field of SPs manifest
Document `boot-order` field from FF-A partitions manifest, in accordance
to Hafnium's (SPM) implementation.
Signed-off-by: J-Alves <joao.alves@arm.com>
docs(ff-a): boot order field of SPs manifest
Document `boot-order` field from FF-A partitions manifest, in accordance
to Hafnium's (SPM) implementation.
Signed-off-by: J-Alves <joao.alves@arm.com>
Change-Id: I9fd070100ee52e0d465d2cce830cc91d78bddfc0
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| 572c8ce2 | 15-Sep-2021 |
Manoj Kumar <manoj.kumar3@arm.com> |
feat(morello): add DTS for Morello SoC platform
Added Morello SoC specific DTS file.
Change-Id: I099e74ec95ed9e1b47f7d5a68b0dd1e251439e11
Signed-off-by: Manoj Kumar <manoj.kumar3@arm.com>
Signed-of
feat(morello): add DTS for Morello SoC platform
Added Morello SoC specific DTS file.
Change-Id: I099e74ec95ed9e1b47f7d5a68b0dd1e251439e11
Signed-off-by: Manoj Kumar <manoj.kumar3@arm.com>
Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
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