Merge changes Icf5e3045,Ie5fb0b72 into integration

* changes:
docs(allwinner): update SoC list and build options
docs(allwinner): add SUNXI_SETUP_REGULATORS build option

Merge changes Ifea8148e,I73559522 into integration

* changes:
fix(morello): include errata workaround for 1868343
fix(errata): workaround for Rainier erratum 1868343

fix(st): manage UART clock and reset only in BL2

As the UART is already initialized, no need to check for UART clock
or reset in next BL. An issue can appear if the next BL device tree
(e.g HW_CONFI

fix(st): manage UART clock and reset only in BL2

As the UART is already initialized, no need to check for UART clock
or reset in next BL. An issue can appear if the next BL device tree
(e.g HW_CONFIG) doesn't use the same clocks or resets (like SCMI ones).

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I044ef2386abe2d3dba5a53c3685440d64ca50a4f

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fix(morello): include errata workaround for 1868343

This patch includes the errata workaround for erratum
1868343 for the Morello platform.

Signed-off-by: Manoj Kumar <manoj.kumar3@arm.com>
Change-

fix(morello): include errata workaround for 1868343

This patch includes the errata workaround for erratum
1868343 for the Morello platform.

Signed-off-by: Manoj Kumar <manoj.kumar3@arm.com>
Change-Id: Ifea8148e10946db2276560f90bf2f32bf12b9dcc

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fix(errata): workaround for Rainier erratum 1868343

Rainier CPU is based on Neoverse N1 R4P0 version which exhibits
the erratum 1868343. This patch inherits the workaround from
neoverse_n1.S file in

fix(errata): workaround for Rainier erratum 1868343

Rainier CPU is based on Neoverse N1 R4P0 version which exhibits
the erratum 1868343. This patch inherits the workaround from
neoverse_n1.S file into rainier.S file for erratum 1868343.

Signed-off-by: Manoj Kumar <manoj.kumar3@arm.com>
Change-Id: I735595229716a77d26369943086de08384cafa70

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Merge changes I19f713de,Ib5bda93d,Id5dafc04,Id20e65e2 into integration

* changes:
feat(plat/rcar3): update IPL and Secure Monitor Rev.3.0.3
feat(plat/rcar3): modify type for Internal function ar

Merge changes I19f713de,Ib5bda93d,Id5dafc04,Id20e65e2 into integration

* changes:
feat(plat/rcar3): update IPL and Secure Monitor Rev.3.0.3
feat(plat/rcar3): modify type for Internal function argument
feat(plat/rcar3): modify sequence for update value for WUPMSKCA57/53
fix(plat/rcar3): fix to bit operation for WUPMSKCA57/53

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Merge "fix(ufs): delete call to inv_dcache_range for utrd" into integration

refactor(st-ddr): move basic tests in a dedicated file

These basic tests are generic and should be used independently of the
driver, depending on the plaftorm characteristics.

Change-Id: I38161b659

refactor(st-ddr): move basic tests in a dedicated file

These basic tests are generic and should be used independently of the
driver, depending on the plaftorm characteristics.

Change-Id: I38161b659ef2a23fd30a56e1c9b1bd98461a2fe4
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@foss.st.com>

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refactor(st-ddr): reorganize generic and specific elements

stm32mp_ddrctl structure contains DDRCTRL registers definitions.
stm32mp_ddr_info contains general DDR information extracted from DT.
stm32

refactor(st-ddr): reorganize generic and specific elements

stm32mp_ddrctl structure contains DDRCTRL registers definitions.
stm32mp_ddr_info contains general DDR information extracted from DT.
stm32mp_ddr_size moves to the generic side.
stm32mp1_ddr_priv contains platform private data.

stm32mp_ddr_dt_get_info() and stm32mp_ddr_dt_get_param() allow to
retrieve data from DT. They are located in new generic c/h files in
which stm32mp_ddr_param structure is declared. Platform makefile
is updated.

Adapt driver with this new classification.

Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Change-Id: I4187376c9fff1a30e7a94407d188391547107997

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feat(stm32mp1): allow configuration of DDR AXI ports number

A new flag STM32MP_DDR_DUAL_AXI_PORT is added, and enabled by default.
It will allow choosing single or dual AXI ports for DDR.

Change-Id

feat(stm32mp1): allow configuration of DDR AXI ports number

A new flag STM32MP_DDR_DUAL_AXI_PORT is added, and enabled by default.
It will allow choosing single or dual AXI ports for DDR.

Change-Id: I48826a66a6f4d18df87e081c0960af89ddda1b9d
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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refactor(st-ddr): update parameter array initialization

Force alignment of the size of parameters array with the expected
value by the binding.
The registers dynamic structs are removed as not used

refactor(st-ddr): update parameter array initialization

Force alignment of the size of parameters array with the expected
value by the binding.
The registers dynamic structs are removed as not used in TF-A.

Change-Id: I7a41f355a435f54fbf23f468cca87c7f8f7e69e8
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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feat(st-ddr): add read valid training support

Add the read data eye training = training for optimal read valid placement
(RVTRN) when the built-in calibration is executed for LPDDR2 and LPDDR3.

Sig

feat(st-ddr): add read valid training support

Add the read data eye training = training for optimal read valid placement
(RVTRN) when the built-in calibration is executed for LPDDR2 and LPDDR3.

Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Change-Id: I7ac1c77c21ebc30315b532741f2f255c2312d5b2

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refactor(stm32mp1): remove the support of calibration result

The support of a predefined DDR PHY tuning result is removed for
STM32MP1 driver because it is not needed at the supported frequency
when

refactor(stm32mp1): remove the support of calibration result

The support of a predefined DDR PHY tuning result is removed for
STM32MP1 driver because it is not needed at the supported frequency
when built-in calibration is executed.

The calibration parameters were provided in the device tree by the
optional node "st,phy-cal", activated in ddr helper file by the
compilation flag DDR_PHY_CAL_SKIP and filled with values generated
by CubeMX.

This patch
- updates the binding file to remove "st,phy-cal" support
- updates the device trees and remove the associated defines
- simplifies the STM32MP1 DDR driver and remove the support of
the optional "st,phy-cal"

After this patch the built-in calibration is always executed.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Change-Id: I3fc445520c259f7f05730aefc25e64b328bf7159

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feat(mt8195): apply erratas of CA78 for MT8195

MT8195 uses Cortex A78 CPU, so we apply these erratas.

TEST=build pass
BUG=none

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I5ce

feat(mt8195): apply erratas of CA78 for MT8195

MT8195 uses Cortex A78 CPU, so we apply these erratas.

TEST=build pass
BUG=none

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I5ce3d5c490a12226bff4eb5a2d55687da0f74f0e

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fix(st-ddr): correct DDR warnings

Replace %d with %u in logs, to avoid warning when
-Wformat-signedness is enabled.
And correct the order of includes.

Change-Id: I7c711a37fc1deceb8853831a8a09ae5042

fix(st-ddr): correct DDR warnings

Replace %d with %u in logs, to avoid warning when
-Wformat-signedness is enabled.
And correct the order of includes.

Change-Id: I7c711a37fc1deceb8853831a8a09ae50422859c9
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>

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Merge "feat(plat/mediatek/mt8195): improve SPM wakeup log" into integration

Merge changes from topic "st_fixes" into integration

* changes:
fix(stm32mp1): do not reopen debug features
refactor(stm32mp1): improve DGBMCU driver
fix(stm32mp1): set reset pulse duration to

Merge changes from topic "st_fixes" into integration

* changes:
fix(stm32mp1): do not reopen debug features
refactor(stm32mp1): improve DGBMCU driver
fix(stm32mp1): set reset pulse duration to 31ms

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Merge "refactor(plat/rockchip/rk3399/drivers/gpio): reduce code duplication" into integration

Merge "fix(st-sdmmc2): check regulator enable/disable return" into integration

refactor(plat/rockchip/rk3399/drivers/gpio): reduce code duplication

Refactor the GPIO code to use a small lookup table instead of redundant or
repetitive code.

Signed-off-by: Jona Stubbe <tf-a@jon

refactor(plat/rockchip/rk3399/drivers/gpio): reduce code duplication

Refactor the GPIO code to use a small lookup table instead of redundant or
repetitive code.

Signed-off-by: Jona Stubbe <tf-a@jona-stubbe.de>
Change-Id: Icf60385095efc1f506e4215d497b60f90e16edfd
Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>

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fix(st-sdmmc2): check regulator enable/disable return

The issue was reported by Coverity [1]. The return of the functions
regulator_disable() and regulator_enable() was not checked.
If they fail, th

fix(st-sdmmc2): check regulator enable/disable return

The issue was reported by Coverity [1]. The return of the functions
regulator_disable() and regulator_enable() was not checked.
If they fail, this means there is an issue either with PMIC or I2C.
The board should the stop booting with a panic().

[1] https://scan4.scan.coverity.com/reports.htm#v47771/p11439/mergedDefectId=374565

Change-Id: If5dfd5643c210e03ae4b1f4cab0168c0db89f60e
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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fix(stm32mp1): do not reopen debug features

On closed chips, it is not allowed to open debug. The BSEC debug
register can not be rewritten.
On open chips, the debug is already open, no need to rewri

fix(stm32mp1): do not reopen debug features

On closed chips, it is not allowed to open debug. The BSEC debug
register can not be rewritten.
On open chips, the debug is already open, no need to rewrite this
register. This part of code is just removed.
An INFO message is displayed if debug is disabled.
The freeze of the watchdog during debug is also removed.
In case of debug, this must be managed by the software that enables
the debugger.

Change-Id: I19fbd3c487bb1018db30fd599cfa94fe5090899f
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>

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refactor(stm32mp1): improve DGBMCU driver

Add function headers to improve readability.
Add asserts when required.
Use RCC_BASE address.

Change-Id: Ia545293f00167b6276331a986ea7aa08c006e004
Signed-o

refactor(stm32mp1): improve DGBMCU driver

Add function headers to improve readability.
Add asserts when required.
Use RCC_BASE address.

Change-Id: Ia545293f00167b6276331a986ea7aa08c006e004
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>

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fix(stm32mp1): set reset pulse duration to 31ms

According to ST Application note AN5256 [1], the minimum reset pulse
duration should be set to 31ms on boards powered with discrete
regulators.

[1] h

fix(stm32mp1): set reset pulse duration to 31ms

According to ST Application note AN5256 [1], the minimum reset pulse
duration should be set to 31ms on boards powered with discrete
regulators.

[1] https://www.st.com/resource/en/application_note/dm00561921.pdf

Change-Id: Ib6ed029ee8a4b95f75a80948fdd2154b4ebe484f
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>

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Merge "feat(allwinner): allow to skip PMIC regulator setup" into integration