refactor(st-gpio): code improvements

No functional, change, but some improvements:
- Declare set_gpio() as static (only called locally)
- Handle the type ('open-drain') property independently from t

refactor(st-gpio): code improvements

No functional, change, but some improvements:
- Declare set_gpio() as static (only called locally)
- Handle the type ('open-drain') property independently from the
mode one.
- Replace mmio_clrbits_32() + mmio_setbits_32() with
mmio_clrsetbits_32().
- Add a missing log
- Add missing U() in macro definitions

Signed-off-by: Fabien Dessenne <fabien.dessenne@foss.st.com>
Change-Id: I1a79609609ac8e8001127ebefdb81def573f76fa

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Merge "docs(commit-style): change blessed scope of FF-A" into integration

feat(stm32mp1): warn when debug enabled on secure chip

Add a banner that inform user that debug is enabled
on a secure chip.

Change-Id: Ib618ac1332b40a1af72d0b60750eea4fc36a8014
Signed-off-by: Lion

feat(stm32mp1): warn when debug enabled on secure chip

Add a banner that inform user that debug is enabled
on a secure chip.

Change-Id: Ib618ac1332b40a1af72d0b60750eea4fc36a8014
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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fix(stm32mp1): rework switch/case for MISRA

Avoid the use of return inside switch/case in stm32mp_is_single_core().
Although this MISRA rulre might not be enforced, we align on what is done
for stm3

fix(stm32mp1): rework switch/case for MISRA

Avoid the use of return inside switch/case in stm32mp_is_single_core().
Although this MISRA rulre might not be enforced, we align on what is done
for stm32mp_is_auth_supported().

Change-Id: I00a5ec1b18c55b4254af00c9c5cf5a4dce104175
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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feat(st): disable authentication based on part_number

STM32MP15xA and STM32MP15xD chip part numbers don't
support the secure boot.
All functions linked to secure boot must not be used
and signed bin

feat(st): disable authentication based on part_number

STM32MP15xA and STM32MP15xD chip part numbers don't
support the secure boot.
All functions linked to secure boot must not be used
and signed binaries are not allowed on such chip.

Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Change-Id: I5b85f322f5eb3b64415e1819bd00fb2c99f20695

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feat(tc): enable SMMU for DPU

The SMMU needs to be enabled to support 8GB RAM

Signed-off-by: Anders Dellien <anders.dellien@arm.com>
Change-Id: Ie81f2fc59886c52e9d6ed799ea73f49eb7a7c307

feat(tc): add reserved memory region for Gralloc

Gralloc for Android S uses dmabuf, we need to add reserved memory area
for these allocations

Signed-off-by: Anders Dellien <anders.dellien@arm.com>

feat(tc): add reserved memory region for Gralloc

Gralloc for Android S uses dmabuf, we need to add reserved memory area
for these allocations

Signed-off-by: Anders Dellien <anders.dellien@arm.com>
Change-Id: If869ac930fadc374ec435cae3847ba374584275b

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feat(tc): enable GPU

Add DTS node for GPU to support hardware rendering in Android

Signed-off-by: Anders Dellien <anders.dellien@arm.com>
Change-Id: I2cf2badf5b15e59a910f6cf7d3d30fdfaf4fe9ce

fix(tc): remove the bootargs node

We need to keep the kernel command line in Yocto, otherwise we
can't support AVB.

Signed-off-by: Anders Dellien <anders.dellien@arm.com>
Change-Id: Ic291eb13620b30

fix(tc): remove the bootargs node

We need to keep the kernel command line in Yocto, otherwise we
can't support AVB.

Signed-off-by: Anders Dellien <anders.dellien@arm.com>
Change-Id: Ic291eb13620b307f10354c2c2797c6fc9b053e83

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Merge changes from topic "st-nvmem" into integration

* changes:
feat(stm32mp1): manage monotonic counter
feat(stm32mp1): new way to access platform OTP
feat(stm32mp1-fdts): update NVMEM nodes

Merge changes from topic "st-nvmem" into integration

* changes:
feat(stm32mp1): manage monotonic counter
feat(stm32mp1): new way to access platform OTP
feat(stm32mp1-fdts): update NVMEM nodes
refactor(st-drivers): improve BSEC driver
feat(stm32mp1-fdts): add nvmem_layout node and OTP definitions
feat(stm32mp1): add NVMEM layout compatibility definition

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Merge changes I25047322,Id476f815 into integration

* changes:
fix(plat/rcar3): change stack size of BL31
fix(plat/rcar3): fix SYSTEM_OFF processing for R-Car D3

Merge "fix(scmi): add missing \n in ERROR message" into integration

refactor(el3-runtime): add prepare_el3_entry func

In the next patch we add an extra step of setting the PSTATE
registers to a known state on el3 entry. In this patch we create
the function prepare_e

refactor(el3-runtime): add prepare_el3_entry func

In the next patch we add an extra step of setting the PSTATE
registers to a known state on el3 entry. In this patch we create
the function prepare_el3_entry to wrap the steps needed for before
el3 entry. For now this is only save_gp_pmcr_pauth_regs.

Change-Id: Ie26dc8d89bfaec308769165d2649e84d41be196c
Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>

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docs(commit-style): change blessed scope of FF-A

Also split SPM MM into it's own scope.

Change-Id: I9cfb1ddec7419ad0d7b539f65e7322bbd44a3913
Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>

feat(stm32mp1): manage monotonic counter

The monotonic counter is stored in an OTP fuse.
A check is done in TF-A.
If the TF-A version is incremented, then the counter will be updated
in the correspo

feat(stm32mp1): manage monotonic counter

The monotonic counter is stored in an OTP fuse.
A check is done in TF-A.
If the TF-A version is incremented, then the counter will be updated
in the corresponding OTP.

Change-Id: I6e7831300ca9efbb35b4c87706f2dcab35affacb
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Mathieu Belou <mathieu.belou@st.com>

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feat(stm32mp1): new way to access platform OTP

Use dt_find_otp_name() to retrieve platform OTP information
from device tree, directly or through stm32_get_otp_index() and
stm32_get_otp_value() platf

feat(stm32mp1): new way to access platform OTP

Use dt_find_otp_name() to retrieve platform OTP information
from device tree, directly or through stm32_get_otp_index() and
stm32_get_otp_value() platform services.
String definitions replace hard-coded values, they are used to call
this new function.

Change-Id: I81213e4a9ad08fddadc2c97b064ae057a4c79561
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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feat(stm32mp1-fdts): update NVMEM nodes

Set non-secure property on platform secure OTP nodes that non-secure
world is allowed to access through secure world services.
These are the SoC MAC address a

feat(stm32mp1-fdts): update NVMEM nodes

Set non-secure property on platform secure OTP nodes that non-secure
world is allowed to access through secure world services.
These are the SoC MAC address and the ST boards board_id OTPs.
Most of these were already done but it was missing for ED1 board.

Change-Id: Idfa6322d9d5c35285706d0b2d32ae09af38684a7
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>

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refactor(st-drivers): improve BSEC driver

Rename driver file to BSEC2.
Split header file in IP and feature parts.
Add functions to access BSEC scratch register.
Several corrections and improvements.

refactor(st-drivers): improve BSEC driver

Rename driver file to BSEC2.
Split header file in IP and feature parts.
Add functions to access BSEC scratch register.
Several corrections and improvements.
Probe the driver earlier, especially to check debug features.

Change-Id: I1981536398d598d67a19d2d7766dacc18de72ec1
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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feat(stm32mp1-fdts): add nvmem_layout node and OTP definitions

A new nvmem_layout node includes nvmem platform-dependent layout
information, such as OTP NVMEM cell lists (phandle, name).
This list a

feat(stm32mp1-fdts): add nvmem_layout node and OTP definitions

A new nvmem_layout node includes nvmem platform-dependent layout
information, such as OTP NVMEM cell lists (phandle, name).
This list allows easy access to OTP offsets defined in BSEC node,
where more OTP definitions with offsets in bytes and length have
been added (replace hard-coded values).
Each board may redefine this list, especially for board_id info.

Change-Id: I910ae671b3bf3320ee6500fecc9ec335ae67bbda
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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feat(stm32mp1): add NVMEM layout compatibility definition

Used by driver parsing this node to get information.

Change-Id: I50623a497157adf7b9da6fafe8d79f6ff58c0ebc
Signed-off-by: Nicolas Le Bayon <

feat(stm32mp1): add NVMEM layout compatibility definition

Used by driver parsing this node to get information.

Change-Id: I50623a497157adf7b9da6fafe8d79f6ff58c0ebc
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>

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Merge "feat(cpu): add library support for Poseidon CPU" into integration

Merge "feat(st-regulator): add support for regulator-always-on" into integration

feat(st-regulator): add support for regulator-always-on

Add support for regulator-always-on at BL2 level as it was supported
before using the regulator framework.

Signed-off-by: Pascal Paillet <p.p

feat(st-regulator): add support for regulator-always-on

Add support for regulator-always-on at BL2 level as it was supported
before using the regulator framework.

Signed-off-by: Pascal Paillet <p.paillet@st.com>
Change-Id: Idb2f4ddc2fdd4e0d31fb33da87c84618aa2e5135

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fix(scmi): add missing \n in ERROR message

Correct ERROR message in scmi_process_message().

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I55e337a3904045aa188975f6a7ed3e989678f571

Merge "fix(stm32mp1-fdts): remove mmc1 alias if not needed" into integration