fix(layerscape): fix build issue of mmap_add_ddr_region_dynamically

Fix build issue of mmap_add_ddr_region_dynamically():
ls_bl2_el3_setup.c:(.text.bl2_plat_preload_setup+0x28): undefined
reference

fix(layerscape): fix build issue of mmap_add_ddr_region_dynamically

Fix build issue of mmap_add_ddr_region_dynamically():
ls_bl2_el3_setup.c:(.text.bl2_plat_preload_setup+0x28): undefined
reference to mmap_add_ddr_region_dynamically

Signed-off-by: Biwen Li <biwen.li@nxp.com>
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I74a8b4c2337fc0646d6acb16ce61755c5efbdf38

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fix(nxp-tools): fix create_pbl print log

Replace bl2_offset with bl2_loc, and fix byte-swapping for
Chassis2 SoC(s) only.

Signed-off-by: Biwen Li <biwen.li@nxp.com>
Signed-off-by: Jiafei Pan <Jiafe

fix(nxp-tools): fix create_pbl print log

Replace bl2_offset with bl2_loc, and fix byte-swapping for
Chassis2 SoC(s) only.

Signed-off-by: Biwen Li <biwen.li@nxp.com>
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: Ieb5fd6468178325bfb6fb89b6c31c75cd9030363

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build(changelog): add new scopes for NXP driver

Add new scope for NXP DDR drivers and GIC drivers.

Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I8ff4d203c474593fe2cff846e0040fc8651b20b6

feat(rme): add dummy platform token to RMMD

Add a dummy platform token to RMMD and return it on request. The
platform token is requested with an SMC with the following parameters:
* Fid (0xC4000

feat(rme): add dummy platform token to RMMD

Add a dummy platform token to RMMD and return it on request. The
platform token is requested with an SMC with the following parameters:
* Fid (0xC40001B3).
* Platform token PA (the platform token is copied at this address by
the monitor). The challenge object needs to be passed by
the caller in this buffer.
* Platform token len.
* Challenge object len.

When calling the SMC, the platform token buffer received by EL3 contains
the challenge object. It is not used on the FVP and is only printed to
the log.

Signed-off-by: Mate Toth-Pal <mate.toth-pal@arm.com>
Signed-off-by: Subhasish Ghosh <subhasish.ghosh@arm.com>
Change-Id: I8b2f1d54426c04e76d7a3baa6b0fbc40b0116348

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Merge "refactor(rme): reorg existing RMMD EL3 service FIDs" into integration

fix(morello): dts: fix stdout-path target

According to the DT spec, stdout-path must either start with the full
path to a node, or with an alias.
"soc_uart0" is neither of them, and consequently the

fix(morello): dts: fix stdout-path target

According to the DT spec, stdout-path must either start with the full
path to a node, or with an alias.
"soc_uart0" is neither of them, and consequently the Linux kernel
complains that it cannot find the root console device when just given
"earlycon" on the kernel command line:
===========
[ 0.000000] OF: fdt: earlycon: stdout-path soc_uart0 not found
===========

Use the already defined "serial0" alias to fix this and make "earlycon"
work in Linux.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Change-Id: Ie0ddb1909160c930af3831246f0140363bc0b5db

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refactor(rme): reorg existing RMMD EL3 service FIDs

This patch reworks the GTSI service implementation in RMMD
such that it is made internal to RMMD. This rework also
lays the ground work for additi

refactor(rme): reorg existing RMMD EL3 service FIDs

This patch reworks the GTSI service implementation in RMMD
such that it is made internal to RMMD. This rework also
lays the ground work for additional RMMD services which
can be invoked from RMM.

The rework renames some of the FID macros to make it
more suited for adding more RMMD services. All the RMM-EL31
service SMCs are now routed via rmmd_rmm_el3_handler().

Signed-off-by: Soby Mathew <soby.mathew@arm.com>
Change-Id: Ic52ca0f33b79a1fd1deefa8136f9586b088b2e07

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fix(errata): workaround for Cortex A78 AE erratum 2395408

Cortex A78 AE erratum 2395408 is a Cat B erratum that applies
to revisions <= r0p1. It is still open.

This erratum states, "A translation t

fix(errata): workaround for Cortex A78 AE erratum 2395408

Cortex A78 AE erratum 2395408 is a Cat B erratum that applies
to revisions <= r0p1. It is still open.

This erratum states, "A translation table walk that matches an
existing L1 prefetch with a read request outstanding on CHI might
fold into the prefetch, which might lead to data corruption for
a future instruction fetch"

This erratum is avoided by setting CPUACTLR2_EL1[40] to 1 to
disable folding of demand requests into older prefetches with
L2 miss requests outstanding.

SDEN is available at https://developer.arm.com/documentation/SDEN-1707912

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: Ic17968987ca3c67fa7f64211bcde6dfcb35ed5d6

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fix(errata): workaround for Cortex A78 AE erratum 2376748

Cortex A78 AE erratum 2376748 is a Cat B erratum that applies
to revisions <= r0p1. It is still open.

The erratum states, "A PE executing a

fix(errata): workaround for Cortex A78 AE erratum 2376748

Cortex A78 AE erratum 2376748 is a Cat B erratum that applies
to revisions <= r0p1. It is still open.

The erratum states, "A PE executing a PLDW or PRFM PST instruction
that lies on a mispredicted branch path might cause a second PE
executing a store exclusive to the same cache line address to fail
continuously."

The erratum is avoided by setting CPUACTLR2_EL1[0] to 1 to force
PLDW/PFRM ST to behave like PLD/PRFM LD and not cause invalidations
to other PE caches. There might be a small performance degradation
to this workaround for certain workloads that share data.

SDEN is available at https://developer.arm.com/documentation/SDEN-1707912

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: I93bd392a870d4584f3e12c8e4626dbe5a3a40a4d

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Merge "build(sptool): handle uuid field in SP layout file" into integration

Merge "fix(security): workaround for CVE-2022-23960 for A76AE, A78AE, A78C" into integration

Merge "fix(tegra194/ras): remove incorrect erxctlr assert" into integration

build(changelog): add new scope for TI platform

Add new scope for TI and K3 platforms.

Change-Id: I3b666c73e3ee8bcf73fcd155b7a372f44b56b033
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>

Merge changes from topic "stm32mp13" into integration

* changes:
feat(stm32mp1): select platform compilation either by flag or DT
feat(stm32mp1-fdts): add support for STM32MP13 DK board
feat(s

Merge changes from topic "stm32mp13" into integration

* changes:
feat(stm32mp1): select platform compilation either by flag or DT
feat(stm32mp1-fdts): add support for STM32MP13 DK board
feat(stm32mp1-fdts): add DDR support for STM32MP13
feat(stm32mp1-fdts): add st-io_policies node for STM32MP13
feat(stm32mp1): updates for STM32MP13 device tree compilation
feat(stm32mp1-fdts): add DT files for STM32MP13
feat(dt-bindings): add TZC400 bindings for STM32MP13
feat(stm32mp1): add "Boot mode" management for STM32MP13
feat(stm32mp1): manage HSLV on STM32MP13
feat(stm32mp1): add sdmmc compatible in platform define
feat(st-sdmmc2): allow compatible to be defined in platform code
feat(stm32mp1): update IO compensation on STM32MP13
feat(stm32mp1): call pmic_voltages_init() in platform init
feat(st-pmic): add pmic_voltages_init() function
feat(stm32mp1): update CFG0 OTP for STM32MP13
feat(stm32mp1): usb descriptor update for STM32MP13
feat(st-clock): add clock driver for STM32MP13
feat(dt-bindings): add bindings for STM32MP13
feat(stm32mp1): get CPU info from SYSCFG on STM32MP13
feat(stm32mp1): use only one filter for TZC400 on STM32MP13
feat(stm32mp1): add a second fixed regulator
feat(stm32mp1): adaptations for STM32MP13 image header
feat(stm32mp1): update boot API for header v2.0
feat(stm32mp1): update IP addresses for STM32MP13
feat(stm32mp1): add part numbers for STM32MP13
feat(stm32mp1): chip rev. Z is 0x1001 on STM32MP13
feat(stm32mp1): update BACKUP_BOOT_MODE for STM32MP13
feat(stm32mp1): stm32mp_is_single_core() for STM32MP13
feat(stm32mp1): remove unsupported features on STM32MP13
feat(stm32mp1): update memory mapping for STM32MP13
feat(stm32mp1): introduce new flag for STM32MP13
feat(st): update stm32image tool for header v2

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Merge "docs(a3k): update documentation about DEBUG mode for UART" into integration

Merge "fix(plat/arm): fix SP count limit without dual root CoT" into integration

Merge changes I1517b69c,Ie01f36ff into integration

* changes:
fix(ufs): move nutrs assignment to ufs_init
refactor(ufs): adds a function for sending command

feat(stm32mp1): select platform compilation either by flag or DT

To choose either STM32MP13 or STM32MP15, one of the two flags can be
set to 1 in the make command line. Or the platform selection can

feat(stm32mp1): select platform compilation either by flag or DT

To choose either STM32MP13 or STM32MP15, one of the two flags can be
set to 1 in the make command line. Or the platform selection can be
done with device tree name, if it begins with stm32mp13 or stm32mp15.

Change-Id: I72f42665c105b71a84b4952ef3fcd6c06ae4598c
Signed-off-by: Lionel Debieve <lionel.debieve@foss.st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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feat(stm32mp1-fdts): add support for STM32MP13 DK board

This stm32mp135f-dk board embeds a STM32MP135F SoC (900MHz / crypto
capabilities) and following peripherals: STPMIC (power delivery), 512MB
DD

feat(stm32mp1-fdts): add support for STM32MP13 DK board

This stm32mp135f-dk board embeds a STM32MP135F SoC (900MHz / crypto
capabilities) and following peripherals: STPMIC (power delivery), 512MB
DDR3L memory, SDcard, dual RMII Ethernet, display H7, RPI connector,
wifi/BT murata combo, USBOTG/STM32G0/TypeC, STMIPID02/CSI OV5640.
Add board DT file taken from kernel.
Add fw-config files for this new board.

Change-Id: I7cce1f8eb39815d7d1df79311bd7ad41061524b8
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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feat(stm32mp1-fdts): add DDR support for STM32MP13

Add dedicated device tree files for STM32MP13.
Add new DDR compatible for STM32MP13x.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.co

feat(stm32mp1-fdts): add DDR support for STM32MP13

Add dedicated device tree files for STM32MP13.
Add new DDR compatible for STM32MP13x.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Change-Id: Ib1bb9ad8cb2ab9f5f81549635d6604093aeb99d3

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feat(stm32mp1-fdts): add st-io_policies node for STM32MP13

To be able to load images with FIP and FCONF on STM32MP13,
the st-io_policies has to be filled.
It is a copy of the node in stm32mp15_bl2.d

feat(stm32mp1-fdts): add st-io_policies node for STM32MP13

To be able to load images with FIP and FCONF on STM32MP13,
the st-io_policies has to be filled.
It is a copy of the node in stm32mp15_bl2.dtsi .

Change-Id: Ia15f50d1179e9b8aefe621dc5e0070ea845d6aac
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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feat(stm32mp1): updates for STM32MP13 device tree compilation

Add stm32mp13_bl2.dtsi files.
Update compilation variables for STM32MP13.

Change-Id: Ia3aa3abfe09c04c1a57541e565c212aa094e285c
Signed-o

feat(stm32mp1): updates for STM32MP13 device tree compilation

Add stm32mp13_bl2.dtsi files.
Update compilation variables for STM32MP13.

Change-Id: Ia3aa3abfe09c04c1a57541e565c212aa094e285c
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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feat(stm32mp1-fdts): add DT files for STM32MP13

STM32MP13 is a single Cortex-A7 CPU, without co-processor.
As for STM32MP15x SoC family, STM32MP15x SoCs come with different
features, depending on So

feat(stm32mp1-fdts): add DT files for STM32MP13

STM32MP13 is a single Cortex-A7 CPU, without co-processor.
As for STM32MP15x SoC family, STM32MP15x SoCs come with different
features, depending on SoC version. Each peripheral node is created.
Some are left empty for the moment , and will be filled later on.

Change-Id: I0166bb70dfa7f717e89e89883b059a5b873c4ef7
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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feat(dt-bindings): add TZC400 bindings for STM32MP13

And new file stm32mp13-tzc400.h is created for STM32MP13.

Change-Id: I18d6aa443d07dc42c0fff56fefb2a47632a2c0e6
Signed-off-by: Yann Gautier <yann

feat(dt-bindings): add TZC400 bindings for STM32MP13

And new file stm32mp13-tzc400.h is created for STM32MP13.

Change-Id: I18d6aa443d07dc42c0fff56fefb2a47632a2c0e6
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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feat(stm32mp1): add "Boot mode" management for STM32MP13

Add new APIs to enter and exit "boot mode".

In this mode a potential tamper won't block access or reset
the secure IPs needed while boot, wi

feat(stm32mp1): add "Boot mode" management for STM32MP13

Add new APIs to enter and exit "boot mode".

In this mode a potential tamper won't block access or reset
the secure IPs needed while boot, without this mode a dead
lock may occurs.

Change-Id: Iad60d4a0420ec125b842a285f73a20eb54cd1828
Signed-off-by: Nicolas Toromanoff <nicolas.toromanoff@st.com>

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