fix(zynqmp): update the log message to verbose

Changing the log message from notice to verbose, to save some space
and that leads to successfull compilation.

Signed-off-by: Venkatesh Yadav Abbarapu

fix(zynqmp): update the log message to verbose

Changing the log message from notice to verbose, to save some space
and that leads to successfull compilation.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Change-Id: Iee5a808febf211464eb8ba6f0377f79378333f5d

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Merge "feat(smmu): configure SMMU Root interface" into integration

fix(security): update Cortex-A15 CPU lib files for CVE-2022-23960

Cortex-A15 does not support FEAT_CSV2 so the existing workaround for
Spectre V2 is sufficient to mitigate against Spectre BHB attack

fix(security): update Cortex-A15 CPU lib files for CVE-2022-23960

Cortex-A15 does not support FEAT_CSV2 so the existing workaround for
Spectre V2 is sufficient to mitigate against Spectre BHB attacks,
however the code needed to be updated to work with the new build flag.

Also, some code was refactored several years ago and not updated in
the Cortex-A15 library file so this patch fixes that as well.

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I768c88a38c561c91019b038ac6c22b291955f18e

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fix(amu): limit virtual offset register access to NS world

Previously the SCR_EL3.AMVOFFEN bit was set for all contexts, this
behavior is incorrect as it allows secure world to access the virtual
of

fix(amu): limit virtual offset register access to NS world

Previously the SCR_EL3.AMVOFFEN bit was set for all contexts, this
behavior is incorrect as it allows secure world to access the virtual
offset registers when it should not be able to. This patch only sets
AMVOFFEN for non-secure world.

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I2c61fe0a8a0092df089f1cb2c0d8a45c8c8ad0d3

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Merge changes I80661161,I82c1fa93,I018ccbb9,Ibc23734d,I97406abe, ... into integration

* changes:
feat(intel): add SMC support for HWMON voltage and temp sensor
feat(intel): add SMC support for G

Merge changes I80661161,I82c1fa93,I018ccbb9,Ibc23734d,I97406abe, ... into integration

* changes:
feat(intel): add SMC support for HWMON voltage and temp sensor
feat(intel): add SMC support for Get USERCODE
fix(intel): extend SDM command to return the SDM firmware version
feat(intel): add SMC for enquiring firmware version
fix(intel): configuration status based on start request
fix(intel): bit-wise configuration flag handling
fix(intel): get config status OK status
fix(intel): use macro as return value
fix(intel): fix fpga config write return mechanism
feat(intel): add SiP service for DCMF status
feat(intel): add RSU 'Max Retry' SiP SMC services
feat(intel): enable SMC SoC FPGA bridges enable/disable
feat(intel): add SMC/PSCI services for DCMF version support
feat(intel): allow to access all register addresses if DEBUG=1
fix(intel): modify how configuration type is handled
feat(intel): support SiP SVC version
feat(intel): enable firewall for OCRAM in BL31
feat(intel): create source file for firewall configuration
fix(intel): refactor NOC header

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feat(smmu): configure SMMU Root interface

This change performs a basic configuration of the SMMU root registers
interface on an RME enabled system. This permits enabling GPC checks
for transactions

feat(smmu): configure SMMU Root interface

This change performs a basic configuration of the SMMU root registers
interface on an RME enabled system. This permits enabling GPC checks
for transactions originated from a non-secure or secure device upstream
to an SMMU. It re-uses the boot time GPT base address and configuration
programmed on the PE.
The root register file offset is platform dependent and has to be
supplied on a model command line.

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I4f889be6b7afc2afb4d1d147c5c1c3ea68f32e07

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Merge "feat(qemu): add support for measured boot" into integration

feat(intel): add SMC support for HWMON voltage and temp sensor

Add support to read temperature and voltage using SMC command

Signed-off-by: Kris Chaplin <kris.chaplin@linux.intel.com>
Signed-off-by

feat(intel): add SMC support for HWMON voltage and temp sensor

Add support to read temperature and voltage using SMC command

Signed-off-by: Kris Chaplin <kris.chaplin@linux.intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I806611610043906b720b5096728a5deb5d652b1d

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feat(intel): add SMC support for Get USERCODE

This patch adds SMC support for enquiring FPGA's User Code.

Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.

feat(intel): add SMC support for Get USERCODE

This patch adds SMC support for enquiring FPGA's User Code.

Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: I82c1fa9390b6f7509b2284d51e199fb8b6a9b1ad

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fix(intel): extend SDM command to return the SDM firmware version

Updates intel_smc_fw_version function to read SDM
firmware version in major/minor ACDS release number.
Update CONFIG_STATUS Response

fix(intel): extend SDM command to return the SDM firmware version

Updates intel_smc_fw_version function to read SDM
firmware version in major/minor ACDS release number.
Update CONFIG_STATUS Response Data [1] bit0-23.

Return INTEL_SIP_SMC_STATUS_ERROR if unexpected
firmware version is being retrieved.

Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I018ccbb961786a75dc6eb873b0f232e71341e1d2

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feat(intel): add SMC for enquiring firmware version

This command allows non-secure world software to enquire the
version of currently running Secure Device Manager (SDM) firmware.

This will be usef

feat(intel): add SMC for enquiring firmware version

This command allows non-secure world software to enquire the
version of currently running Secure Device Manager (SDM) firmware.

This will be useful in maintaining backward-compatibility as well
as ensuring software cross-compabitility.

Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: Ibc23734d1135db74423da5e29655f9d32472a3b0

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fix(intel): configuration status based on start request

Configuration status command now returns the result based on the last
config start command made to the runtime software. The status type can
b

fix(intel): configuration status based on start request

Configuration status command now returns the result based on the last
config start command made to the runtime software. The status type can
be either:
- NO_REQUEST (default)
- RECONFIGURATION
- BITSTREAM_AUTH

Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I97406abe09b49b9d9a5b43e62fe09eb23c729bff
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>

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fix(intel): bit-wise configuration flag handling

Change configuration type handling to bit-wise flag. This is to align
with Linux's FPGA Manager definitions and promotes better compatibility.

Signe

fix(intel): bit-wise configuration flag handling

Change configuration type handling to bit-wise flag. This is to align
with Linux's FPGA Manager definitions and promotes better compatibility.

Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: I5aaf91d3fec538fe3f4fe8395d9adb47ec969434

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fix(intel): get config status OK status

Config status have different OK requirement between MBOX_CONFIG_STATUS
and MBOX_RECONFIG_STATUS request. This patch adds the checking to
differentiate between

fix(intel): get config status OK status

Config status have different OK requirement between MBOX_CONFIG_STATUS
and MBOX_RECONFIG_STATUS request. This patch adds the checking to
differentiate between both command.

Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I45a4c3de460b031757dbcbd0b3a8055cb0a55aff
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>

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fix(intel): use macro as return value

SMC function should strictly return INTEL_SIP_SMC_STATUS macro. Directly
returning value of variable status might cause confusion in calling
software.

Signed-o

fix(intel): use macro as return value

SMC function should strictly return INTEL_SIP_SMC_STATUS macro. Directly
returning value of variable status might cause confusion in calling
software.

Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: Iea17f4feaa5c917e8b995471f3019dba6ea8dcd3
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>

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Merge changes from topic "vendor_makefile_extension" into integration

* changes:
feat(plat/mediatek/build_helpers): introduce mtk makefile
build(makefile): add extra makefile variable for extens

Merge changes from topic "vendor_makefile_extension" into integration

* changes:
feat(plat/mediatek/build_helpers): introduce mtk makefile
build(makefile): add extra makefile variable for extension

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fix(intel): fix fpga config write return mechanism

This revert commit 279c8015fefcb544eb311b9052f417fc02ab84aa.
The previous change breaks this feature compatibility with Linux driver.
Hence, the fi

fix(intel): fix fpga config write return mechanism

This revert commit 279c8015fefcb544eb311b9052f417fc02ab84aa.
The previous change breaks this feature compatibility with Linux driver.
Hence, the fix for the earlier issue is going to be fixed in uboot instead.

Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: I93220243bad65ed53322050d990544c7df4ce66b

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feat(intel): add SiP service for DCMF status

This patch adds 2 additional RSU SiP services for Intel SoCFPGA
platforms:
- INTEL_SIP_SMC_RSU_COPY_DCMF_STATUS stores current DCMF status in
BL31
- IN

feat(intel): add SiP service for DCMF status

This patch adds 2 additional RSU SiP services for Intel SoCFPGA
platforms:
- INTEL_SIP_SMC_RSU_COPY_DCMF_STATUS stores current DCMF status in
BL31
- INTEL_SIP_SMC_RSU_DCMF_STATUS is calling function for non-secure
software to retrieve stored DCMF status

Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: Ic7a3e6988c71ad4bf66c58a1d669956524dfdf11

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Merge "docs(build): update GCC to version 11.2-2022.02" into integration

Merge changes from topic "qemu-measured-boot" into integration

* changes:
fix(arm): fix fvp and juno build with USE_ROMLIB option
feat(fdt-wrappers): add function to find or add a sudnode

feat(intel): add RSU 'Max Retry' SiP SMC services

Add SiP SMC services to store/retrieve 'Max Retry' counter
for Remote System Update (RSU).

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
S

feat(intel): add RSU 'Max Retry' SiP SMC services

Add SiP SMC services to store/retrieve 'Max Retry' counter
for Remote System Update (RSU).

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I17c1f0107ead64e6160954d26407f399003bcbd9

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Merge "fix(bl2): define RAM_NOLOAD for XIP" into integration

Merge changes from topic "ti-k3-system-suspend-base-support" into integration

* changes:
feat(ti): allow build config of low power mode support
feat(ti): increase SEC_SRAM_SIZE to 128k
feat(ti

Merge changes from topic "ti-k3-system-suspend-base-support" into integration

* changes:
feat(ti): allow build config of low power mode support
feat(ti): increase SEC_SRAM_SIZE to 128k
feat(ti): add PSCI handlers for system suspend
feat(ti): add gic save and restore calls
feat(ti): add enter sleep method

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feat(qemu): add support for measured boot

Add helper functions to generate event log for qemu
when MEASURED_BOOT=1.

Signed-off-by: Ruchika Gupta <ruchika.gupta@linaro.org>
Change-Id: I17a098cb614a3

feat(qemu): add support for measured boot

Add helper functions to generate event log for qemu
when MEASURED_BOOT=1.

Signed-off-by: Ruchika Gupta <ruchika.gupta@linaro.org>
Change-Id: I17a098cb614a3a89fe0fe9577bed6edda8bfd070

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fix(arm): fix fvp and juno build with USE_ROMLIB option

Change-Id: I8a9b30a952be594435003f0d684e3faad484e8b8
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>