fix(zynqmp): resolve misra R14.4 warnings

MISRA Violation: MISRA-C:2012 R.14.4
The controlling expression of an if statement and the controlling
expression of an iteration-statement shall have essen

fix(zynqmp): resolve misra R14.4 warnings

MISRA Violation: MISRA-C:2012 R.14.4
The controlling expression of an if statement and the controlling
expression of an iteration-statement shall have essentially Boolean type.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Change-Id: I8f3f6f956d1d58ca201fb5895f12bcaabf2afd3b

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fix(zynqmp): resolve misra R16.3 warnings

MISRA Violation: MISRA-C:2012 R.16.3
- An unconditional break statement shall terminate every switch-clause.

Signed-off-by: Venkatesh Yadav Abbarapu <venka

fix(zynqmp): resolve misra R16.3 warnings

MISRA Violation: MISRA-C:2012 R.16.3
- An unconditional break statement shall terminate every switch-clause.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Change-Id: I96a8b627c593ff1293b725d443531e42368923c5

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fix(zynqmp): resolve misra R15.7 warnings

MISRA Violation: MISRA-C:2012 R.15.7
- All if . . else if constructs shall be terminated
with an else statement.

Signed-off-by: Venkatesh Yadav Abbarapu <v

fix(zynqmp): resolve misra R15.7 warnings

MISRA Violation: MISRA-C:2012 R.15.7
- All if . . else if constructs shall be terminated
with an else statement.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Change-Id: If921ca7c30b2feea6535791aa15f4de7101c3134

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fix(zynqmp): resolve misra R15.6 warnings

MISRA Violation: MISRA-C:2012 R.15.6
- The body of an iteration-statement or a selection-statement shall be
a compound statement.

Signed-off-by: Venkates

fix(zynqmp): resolve misra R15.6 warnings

MISRA Violation: MISRA-C:2012 R.15.6
- The body of an iteration-statement or a selection-statement shall be
a compound statement.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Change-Id: I0fc8eeac0e592f00297a1ac42a1ba3df1144733b

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fix(zynqmp): resolve misra 7.2 warnings

MISRA Violation: MISRA-C:2012 R.7.2
- A "u" or "U" suffix shall be applied to all integer constants that are
represented in an unsigned type.

Signed-off-by:

fix(zynqmp): resolve misra 7.2 warnings

MISRA Violation: MISRA-C:2012 R.7.2
- A "u" or "U" suffix shall be applied to all integer constants that are
represented in an unsigned type.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Change-Id: Ieeff81ed42155c03aebca75b2f33f311279b9ed4

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fix(zynqmp): resolve misra R10.3

MISRA Violation: MISRA-C:2012 R.10.3
- The value of an expression shall not be assigned to an object with a
narrower essential type or of a different essential typ

fix(zynqmp): resolve misra R10.3

MISRA Violation: MISRA-C:2012 R.10.3
- The value of an expression shall not be assigned to an object with a
narrower essential type or of a different essential type category.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Change-Id: I5a60c66788d59e45f41ceb81758b42ef2df9f5f7

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Merge "fix(fvp): fix NULL pointer dereference issue" into integration

Merge "docs(maintainers): update measured boot code owners" into integration

feat(brbe): add BRBE support for NS world

This patch enables access to the branch record buffer control registers
in non-secure EL2 and EL1 using the new build option ENABLE_BRBE_FOR_NS.
It is disab

feat(brbe): add BRBE support for NS world

This patch enables access to the branch record buffer control registers
in non-secure EL2 and EL1 using the new build option ENABLE_BRBE_FOR_NS.
It is disabled for all secure world, and cannot be used with ENABLE_RME.

This option is disabled by default, however, the FVP platform makefile
enables it for FVP builds.

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I576a49d446a8a73286ea6417c16bd0b8de71fca0

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fix(security): report CVE 2022 23960 missing for aarch32 A57 and A72

Since there is no product deployed running EL3 in AArch32 mode for
Cortex-A57 and Cortex-A72, report the workaround for CVE 2022

fix(security): report CVE 2022 23960 missing for aarch32 A57 and A72

Since there is no product deployed running EL3 in AArch32 mode for
Cortex-A57 and Cortex-A72, report the workaround for CVE 2022 23960
as missing on these cores.

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I14d202c1179707257086ad0c4795c397e566b3e6

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feat(intel): add SMPLSEL and DRVSEL setup for Stratix 10 MMC

SMPLSEL and DRVSEL values need to updated in
DWMMC for the IP to work correctly. This apply
on Stratix 10 device only.

Signed-off-by: Lo

feat(intel): add SMPLSEL and DRVSEL setup for Stratix 10 MMC

SMPLSEL and DRVSEL values need to updated in
DWMMC for the IP to work correctly. This apply
on Stratix 10 device only.

Signed-off-by: Loh Tien Hock <tien.hock.loh@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: Ibd799a65890690682e27e4cbbc85e83ea03d51fc

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feat(intel): add support for F2S and S2F bridge SMC with mask to enable, disable and reset bridge

This adds F2S and S2F bridge enable, disable and reset
sequence to enable, disable and reset properl

feat(intel): add support for F2S and S2F bridge SMC with mask to enable, disable and reset bridge

This adds F2S and S2F bridge enable, disable and reset
sequence to enable, disable and reset properly the bridges
in SMC call or during reset.

The reset is also maskable as the SMC from uboot can
pass in the bridge mask when requesting for bridge
enable or disable.

Signed-off-by: Loh Tien Hock <tien.hock.loh@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: Ie144518c591664ef880016c9b3706968411bbf21

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Merge "fix(intel): reject non 4-byte align request size for FPGA Crypto Service (FCS)" into integration

fix(fvp): fix NULL pointer dereference issue

Fixed below NULL pointer dereference issue reported by coverity scan
by asserting the hw_config_info is not NULL.

*** CID 378361: Null pointer derefere

fix(fvp): fix NULL pointer dereference issue

Fixed below NULL pointer dereference issue reported by coverity scan
by asserting the hw_config_info is not NULL.

*** CID 378361: Null pointer dereferences (NULL_RETURNS)
/plat/arm/board/fvp/fvp_bl2_setup.c: 84 in plat_get_next_bl_params()
78
79 /* To retrieve actual size of the HW_CONFIG */
80 param_node = get_bl_mem_params_node(HW_CONFIG_ID);
81 assert(param_node != NULL);
82
83 /* Copy HW config from Secure address to NS address */
>>> CID 378361: Null pointer dereferences (NULL_RETURNS)
>>> Dereferencing "hw_config_info", which is known to be "NULL".
84 memcpy((void *)hw_config_info->ns_config_addr,
85 (void *)hw_config_info->config_addr,
86 (size_t)param_node->image_info.image_size);

Signed-off-by: Manish V Badarkhe <manish.badarkhe@arm.com>
Change-Id: Iaf584044cfc3b2583862bcc1be825966eaffd38e

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feat(spmc): enable checking of execution ctx count

This is a mandatory entry in an SP's manifest however
currently an S-EL1 partition running under the EL3 SPMC
must have the same amount of executio

feat(spmc): enable checking of execution ctx count

This is a mandatory entry in an SP's manifest however
currently an S-EL1 partition running under the EL3 SPMC
must have the same amount of execution contexts as
physical cores therefore just check the entry matches
this value.

Signed-off-by: Marc Bonnici <marc.bonnici@arm.com>
Change-Id: I4c2a85ccde7a7bb9b1232cf6389a8c532cbf3d41

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feat(spmc): enable parsing of UUID from SP Manifest

To align with other SPMC implementations parse the UUID
from the SP manifest as 4 uint32 values and store
this internally.

Change-Id: I7de5d5ef8d

feat(spmc): enable parsing of UUID from SP Manifest

To align with other SPMC implementations parse the UUID
from the SP manifest as 4 uint32 values and store
this internally.

Change-Id: I7de5d5ef8d98dc14bc7c76892133c2333358a379
Signed-off-by: Marc Bonnici <marc.bonnici@arm.com>

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feat(spmc): add partition mailbox structs

Add mailbox structs to the partition descriptors
and ensure these are initialised correctly.

Change-Id: Ie80166d19763c266b6a1d23e351d312dc31fb221
Signed-of

feat(spmc): add partition mailbox structs

Add mailbox structs to the partition descriptors
and ensure these are initialised correctly.

Change-Id: Ie80166d19763c266b6a1d23e351d312dc31fb221
Signed-off-by: Marc Bonnici <marc.bonnici@arm.com>

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feat(plat/arm): allow BL32 specific defines to be used by SPMC_AT_EL3

For EL3 SPMC configuration enabled platforms, allow the reuse of
BL32 specific definitions.

Signed-off-by: Marc Bonnici <marc.b

feat(plat/arm): allow BL32 specific defines to be used by SPMC_AT_EL3

For EL3 SPMC configuration enabled platforms, allow the reuse of
BL32 specific definitions.

Signed-off-by: Marc Bonnici <marc.bonnici@arm.com>
Change-Id: I37ffbbf680326c101fbb2f146085a96c138f07a1

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feat(plat/fvp): add EL3 SPMC #defines

Introduce additional #defines for running with the EL3
SPMC on the FVP.

The increase in xlat tables has been chosen to allow
the test cases to complete success

feat(plat/fvp): add EL3 SPMC #defines

Introduce additional #defines for running with the EL3
SPMC on the FVP.

The increase in xlat tables has been chosen to allow
the test cases to complete successfully and may need
adjusting depending on the desired usecase.

Signed-off-by: Marc Bonnici <marc.bonnici@arm.com>
Change-Id: I7f44344ff8b74ae8907d53ebb652ff8def2d2562

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test(plat/fvp/lsp): add example logical partition

Add an example logical partition to the FVP platform that
simply prints and echos the contents of a direct request
with the appropriate direct respo

test(plat/fvp/lsp): add example logical partition

Add an example logical partition to the FVP platform that
simply prints and echos the contents of a direct request
with the appropriate direct response.

Change-Id: Ib2052c9a63a74830e5e83bd8c128c5f9b0d94658
Signed-off-by: Marc Bonnici <marc.bonnici@arm.com>

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Merge changes from topic "mp/delete_platforms" into integration

* changes:
refactor(mt6795): remove mediatek's mt6795 platform
refactor(sgm775): remove Arm sgm775 platform

Merge "docs(maintainers): add code owners for Firmware Update driver" into integration

docs(maintainers): add code owners for Firmware Update driver

Added myself and Sandrine Bailleux as code owners for Firmware
Update driver.

Signed-off-by: Manish V Badarkhe <manish.badarkhe@arm.com

docs(maintainers): add code owners for Firmware Update driver

Added myself and Sandrine Bailleux as code owners for Firmware
Update driver.

Signed-off-by: Manish V Badarkhe <manish.badarkhe@arm.com>
Change-Id: I34fad895c6236fedc814fb6da4b04fd7fbed9227

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fix(sptool): update Optee FF-A manifest

Change the OPTEE FF-A manifest to comply with changes to the sp pkg [1].
The sptool packs the image at the default offset of 0x4000, if it is not
provided in

fix(sptool): update Optee FF-A manifest

Change the OPTEE FF-A manifest to comply with changes to the sp pkg [1].
The sptool packs the image at the default offset of 0x4000, if it is not
provided in the arguments.

[1] https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/14507

Signed-off-by: J-Alves <joao.alves@arm.com>
Change-Id: I647950410114f7fc24926696212bb7f8101390ac

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feat(sptool): delete c version of the sptool

Change-Id: I224762ef66624c78dd87729dac80b2c956ee50ba
Signed-off-by: J-Alves <joao.alves@arm.com>