Merge "fix(versal): remove clock related macros" into integration

Merge "docs(maintainers): switch emails from Xilinx to AMD" into integration

docs(maintainers): switch emails from Xilinx to AMD

Switch emails from Xilinx to AMD after acquisition.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Change-Id: I5d126dc49e53f2735bb7e103f8f883

docs(maintainers): switch emails from Xilinx to AMD

Switch emails from Xilinx to AMD after acquisition.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Change-Id: I5d126dc49e53f2735bb7e103f8f883a9474206fc

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fix(versal): remove clock related macros

TF-A doesn't configure clock on Versal. Setup is done by previous
bootloader (called PLM) that's why there is no need to have macro listed in
headers. Also p

fix(versal): remove clock related macros

TF-A doesn't configure clock on Versal. Setup is done by previous
bootloader (called PLM) that's why there is no need to have macro listed in
headers. Also previous phase can disable access to these registers that's
why better to remove them.

Change-Id: I53ba344ad932c532b0babdce9d2b26e4c2c1b846
Signed-off-by: Michal Simek <michal.simek@amd.com>

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feat(tc): introduce TC2 platform

Added a platform support to use tc2 specific CPU cores.

Signed-off-by: Rupinderjit Singh <rupinderjit.singh@arm.com>
Change-Id: Ib76d440e358e9bd1cf80aec5b8591f7a6e4

feat(tc): introduce TC2 platform

Added a platform support to use tc2 specific CPU cores.

Signed-off-by: Rupinderjit Singh <rupinderjit.singh@arm.com>
Change-Id: Ib76d440e358e9bd1cf80aec5b8591f7a6e47ecbd

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Merge "fix(psci): fix MISRA failure - Memory - illegal accesses" into integration

fix(psci): fix MISRA failure - Memory - illegal accesses

Fixed below MISRA failure -
>>> CID 379362: Memory - illegal accesses (OVERRUN)
>>> Overrunning array "psci_non_cpu_pd_nodes" of 5

fix(psci): fix MISRA failure - Memory - illegal accesses

Fixed below MISRA failure -
>>> CID 379362: Memory - illegal accesses (OVERRUN)
>>> Overrunning array "psci_non_cpu_pd_nodes" of 5 16-byte
>>> elements at element index 5 (byte offset 95) using index
>>> "i" (which evaluates to 5).

Change-Id: Ie88fc555e48b06563372bfe4e51f16b13c0a020b
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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Merge "fix(doc): document missing RMM-EL3 runtime services" into integration

Merge "fix(errata): workaround for Cortex-X2 erratum 2371105" into integration

fix(errata): workaround for Cortex-X2 erratum 2371105

Cortex-X2 erratum 2371105 is a cat B erratum that applies to
revisions r0p0 - r2p0 and is fixed in r2p1. The workaround is to
set bit[40] of CPU

fix(errata): workaround for Cortex-X2 erratum 2371105

Cortex-X2 erratum 2371105 is a cat B erratum that applies to
revisions r0p0 - r2p0 and is fixed in r2p1. The workaround is to
set bit[40] of CPUACTLR2_EL1 to disable folding of demand requests
into older prefetches with L2 miss requests outstanding.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN1775100/latest

Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: Ib4f0caac36e1ecf049871acdea45526b394b7bad

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Merge "fix(errata): workaround for Cortex A78C erratum 2242638" into integration

Merge "fix(tc): tc2 bl1 start address shifted by one page" into integration

fix(doc): document missing RMM-EL3 runtime services

This patch adds documentation for the missing RMM-EL3
runtime services:

* RMM_RMI_REQ_COMPLETE
* RMM_GTSI_DELEGATE
* RMM_GTSI_UNDELEGATE

This pa

fix(doc): document missing RMM-EL3 runtime services

This patch adds documentation for the missing RMM-EL3
runtime services:

* RMM_RMI_REQ_COMPLETE
* RMM_GTSI_DELEGATE
* RMM_GTSI_UNDELEGATE

This patch also fixes a couple of minor bugs on return codes
for delegate/undelegate internal APIs.

Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com>
Change-Id: Ic721005e7851e838eebaee7865ba78fadc3309e4

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Merge "feat(psci): add a helper function to ensure that non-boot PEs are offline" into integration

fix(tc): tc2 bl1 start address shifted by one page

Change [1] is specific to TC2 model and breaks former TC0/TC1 test
configs.
BL1 start address is 0x0 on TC0/TC1 and 0x1000 from TC2 onwards.
Fix by

fix(tc): tc2 bl1 start address shifted by one page

Change [1] is specific to TC2 model and breaks former TC0/TC1 test
configs.
BL1 start address is 0x0 on TC0/TC1 and 0x1000 from TC2 onwards.
Fix by adding conditional defines depending on TARGET_PLATFORM build
flag.

[1] https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/15917

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I51f77e6a61ca8eaa6871c19cabe9deb1288f5a9d

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feat(psci): add a helper function to ensure that non-boot PEs are offline

Introduce a helper function that ensures that non-boot PEs are offline.
This function will be used by DRTM implementation to

feat(psci): add a helper function to ensure that non-boot PEs are offline

Introduce a helper function that ensures that non-boot PEs are offline.
This function will be used by DRTM implementation to ensure that system
is running with only single PE.

Signed-off-by: Manish V Badarkhe <manish.badarkhe@arm.com>
Signed-off-by: Lucian Paul-Trifu <lucian.paultrifu@gmail.com>
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: I521ebefa49297026b02554629b1710a232148e01

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Merge "fix(errata): workaround for Cortex-A710 erratum 2371105" into integration

Merge "feat(versal): resolve the misra 10.1 warnings" into integration

feat(versal): resolve the misra 10.1 warnings

MISRA Violation: MISRA-C:2012 R.10.1
-The operand to the operator does not have an essentially unsigned type.

Signed-off-by: Venkatesh Yadav Abbarapu <

feat(versal): resolve the misra 10.1 warnings

MISRA Violation: MISRA-C:2012 R.10.1
-The operand to the operator does not have an essentially unsigned type.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Change-Id: I9cde2f1ebceaad8a41c69489ef1d2e6f21f04ed1

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fix(errata): workaround for Cortex-A710 erratum 2371105

Cortex-A710 erratum 2371105 is a cat B erratum that applies to
revisions r0p0 - r2p0 and is fixed in r2p1. The workaround is to
set bit[40] of

fix(errata): workaround for Cortex-A710 erratum 2371105

Cortex-A710 erratum 2371105 is a cat B erratum that applies to
revisions r0p0 - r2p0 and is fixed in r2p1. The workaround is to
set bit[40] of CPUACTLR2_EL1 to disable folding of demand requests
into older prefetches with L2 miss requests outstanding.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN1775101/latest

Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: I342b095b66f808bd6c066c20c581df5341bb7c2c

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fix(errata): workaround for Cortex A78C erratum 2242638

Cortex A78C erratum 2242638 is a Cat B erratum which applies to
revisions r0p1, r0p2 and is still open. The workaround is to apply
a CPU imple

fix(errata): workaround for Cortex A78C erratum 2242638

Cortex A78C erratum 2242638 is a Cat B erratum which applies to
revisions r0p1, r0p2 and is still open. The workaround is to apply
a CPU implementation specific specific patch sequence.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN2004089/latest

Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: I35d385245a04a39b87be71c1a42312f75e1152e5

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Merge "feat(versal): get the handoff params using IPI" into integration

Merge "refactor(xilinx): move the atf handoff structure" into integration

Merge "refactor(versal): move payload and module ID macros" into integration

fix(morello): dts: remove #a-c and #s-c from memory node

The #address-cells and #size-cells properties affect the size of reg
properties in *child* nodes only, they have no effect on the current
nod

fix(morello): dts: remove #a-c and #s-c from memory node

The #address-cells and #size-cells properties affect the size of reg
properties in *child* nodes only, they have no effect on the current
node.

The /memory node has no children, hence there is no need to specify
those properties. dt-validate complains about this:
==========
morello-soc.dtb: /: memory@80000000: '#address-cells', '#size-cells' do
not match any of the regexes: 'pinctrl-[0-9]+'
From schema: dt-schema.git/dtschema/schemas/memory.yaml
==========

Remove the unneeded properties.

Change-Id: I35058a00fa9bfa1007f31a4c21898dd45c586aa8
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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