fix(versal): use only one space for indentation

Trivial patch to remove additional space.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Change-Id: Ifa33dee81243c0b21ca0f13b8e4d575646818162

fix: make TF-A use provided OpenSSL binary

Currently Tf-A uses whatever openssl binary is on the system to sign
images. However if OPENSSL_DIR is specified in the build flags this can
lead to linkin

fix: make TF-A use provided OpenSSL binary

Currently Tf-A uses whatever openssl binary is on the system to sign
images. However if OPENSSL_DIR is specified in the build flags this can
lead to linking issues as the system binary can end up being linked
against shared libraries provided in OPENSSL_DIR/lib if both binaries
(the system's and the on in OPENSSL_DIR/bin) are the same version.
This patch ensures that the binary used is always the one given by
OPENSSL_DIR to avoid those link issues.

Signed-off-by: Salome Thirot <salome.thirot@arm.com>
Change-Id: Ib534e06ebc8482e4391e376d3791a87968de4a99

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fix(versal): fix code indentation issues

Next line should be aligned with the previous code.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Change-Id: I20d82ba5fa70fa252341b62e57fac265241f3391

fix(versal): fix macro coding style issues

Use only one space between #define and macro name.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Change-Id: Ieb9bdd5bcfa56bd265df72692a09c7340fe132cb

fix(bl31): pass the EA bit to 'delegate_sync_ea'

During a synchronous exception, the 'enter_lower_el_sync_ea' handler
tests the ESR_EL3 EA bit and calls 'report_unhandled_exception', if
it is not se

fix(bl31): pass the EA bit to 'delegate_sync_ea'

During a synchronous exception, the 'enter_lower_el_sync_ea' handler
tests the ESR_EL3 EA bit and calls 'report_unhandled_exception', if
it is not set.

EA = 0 and IFSC = SEA, seems to be a contradiction. EA provides further
classification of a synchronous abort. A synchronous abort is determined
by the IFSC value on an instruction fetch synchronous abort. As a result,
EA will never be set to 1 on an instruction fetch synchronous abort and
'report_unhandled_exception' should not be called.

This patch removes this behavior to allow the platform to handle the
exception.

Signed-off-by: Nicolas Benech <nbenech@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: I3f004447ad4316d81649063e1ffb3ac644c83ede

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feat(bl): add interface to query TF-A semantic ver

Adding interface for stand-alone semantic version of TF-A
for exporting to RSS attestation, and potentially other areas
as well.

Signed-off-by: La

feat(bl): add interface to query TF-A semantic ver

Adding interface for stand-alone semantic version of TF-A
for exporting to RSS attestation, and potentially other areas
as well.

Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: Ib4a2c47aa1e42a3b850185e674c90708a05cda53

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Merge "feat(plat/qti): fix to support cpu errata" into integration

Merge changes from topic "st_fip_uuid" into integration

* changes:
feat(stm32mp1): retrieve FIP partition by type UUID
feat(guid-partition): allow to find partition by type UUID
refactor(stm32

Merge changes from topic "st_fip_uuid" into integration

* changes:
feat(stm32mp1): retrieve FIP partition by type UUID
feat(guid-partition): allow to find partition by type UUID
refactor(stm32mp1): update PLAT_PARTITION_MAX_ENTRIES

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Merge "feat(zynqmp): protect eFuses from non-secure access" into integration

Merge changes from topic "xlnx_misra" into integration

* changes:
fix(versal): resolve misra 10.1 warnings
fix(versal): resolve the misra 4.6 warnings

fix(ufs): init utrlba/utrlbau with desc_base

Initialising these registers with header address will not work when
get_empty_slot returns anything other than 0 because these registers
should point to

fix(ufs): init utrlba/utrlbau with desc_base

Initialising these registers with header address will not work when
get_empty_slot returns anything other than 0 because these registers
should point to the starting of transfer request list instead of the
current descriptor

Change-Id: I60b3b59e2be6e2635a59b14dd1f11d93b9d95a1f
Signed-off-by: anans <anans@google.com>

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fix(ufs): fix slot base address computation

The entire packet including UPIUs and PRDT is 0x400 but the controller
just looks for the header (32-bytes) from the UTRL

Change-Id: Ibd5d22b4a841c107fdf

fix(ufs): fix slot base address computation

The entire packet including UPIUs and PRDT is 0x400 but the controller
just looks for the header (32-bytes) from the UTRL

Change-Id: Ibd5d22b4a841c107fdf6447d598c5c600998e0f8
Signed-off-by: Anand Saminathan <anans@google.com>

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fix(versal): resolve misra 10.1 warnings

MISRA Violation: MISRA-C: 2012 R.10.1
-The operand to the operator does not have an essentially
unsigned type.

Signed-off-by: Venkatesh Yadav Abbarapu <venk

fix(versal): resolve misra 10.1 warnings

MISRA Violation: MISRA-C: 2012 R.10.1
-The operand to the operator does not have an essentially
unsigned type.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Change-Id: I4873a620086dfd6f636fe730165a9d13a29e9652

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fix(versal): resolve the misra 4.6 warnings

MISRA Violation: MISRA-C:2012 R.4.6
- Using basic numerical type int rather than a typedef
that includes size and signedness information.

Signed-off-by:

fix(versal): resolve the misra 4.6 warnings

MISRA Violation: MISRA-C:2012 R.4.6
- Using basic numerical type int rather than a typedef
that includes size and signedness information.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Change-Id: Ieff90b5311a3bde8a2cb302ca81c23eeee6d235a

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feat(zynqmp): protect eFuses from non-secure access

When configuration option ZYNQMP_SECURE_EFUSES is defined then Xilinx
ZynqMP's PS eFuses can only be accesses from secure state.

This enables eFu

feat(zynqmp): protect eFuses from non-secure access

When configuration option ZYNQMP_SECURE_EFUSES is defined then Xilinx
ZynqMP's PS eFuses can only be accesses from secure state.

This enables eFuses to be reserved and protected only for security use
cases for example in OP-TEE.

Change-Id: I866905e35ce488f50f5f6e1b4667b08a9fa2386d
Signed-off-by: Vesa Jääskeläinen <vesa.jaaskelainen@vaisala.com>

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feat(plat/qti): fix to support cpu errata

fix to support ARM CPU errata based on core used.

Signed-off-by: Saurabh Gorecha <quic_sgorecha@quicinc.com>
Change-Id: If1a438f98f743435a7a0b683a32ccf1416

feat(plat/qti): fix to support cpu errata

fix to support ARM CPU errata based on core used.

Signed-off-by: Saurabh Gorecha <quic_sgorecha@quicinc.com>
Change-Id: If1a438f98f743435a7a0b683a32ccf14164db37e

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feat(gicv3): validate multichip data for GIC-700

This patch introduces support to validate the GIC-700 multichip data
structure passed by the platform.

GIC-700 provides support for SPI ID 4096 to 5

feat(gicv3): validate multichip data for GIC-700

This patch introduces support to validate the GIC-700 multichip data
structure passed by the platform.

GIC-700 provides support for SPI ID 4096 to 5119. Platforms using the
GIC-700 in a multichip configuration can enable these SPI IDs. The
driver needs to validate the data before using it and this patch
implements the support.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: I6f85ec21ef7a59f397fcf6271f8c13c24fe47697

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Merge "fix(xilinx): miscellaneous fixes for xilinx platforms" into integration

fix(xilinx): miscellaneous fixes for xilinx platforms

This patch gathers miscellaneous minor fixes to the xilinx
platforms like tabs for indentation and misra 10.1 warnings.

Signed-off-by: Michal S

fix(xilinx): miscellaneous fixes for xilinx platforms

This patch gathers miscellaneous minor fixes to the xilinx
platforms like tabs for indentation and misra 10.1 warnings.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Change-Id: I4cdb89ffec7d5abc64e065ed5b5e5d10b30ab9f9

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Merge "fix(ufs): add retries to ufs_read_capacity" into integration

Merge "fix(ufs): point utrlbau to header instead of upiu" into integration

fix(ufs): point utrlbau to header instead of upiu

utrlbau should point to header and not upiu
this is the case everywhere except for ufs_prepare_cmd

Signed-off-by: anans <anans@google.com>
Change-I

fix(ufs): point utrlbau to header instead of upiu

utrlbau should point to header and not upiu
this is the case everywhere except for ufs_prepare_cmd

Signed-off-by: anans <anans@google.com>
Change-Id: I02695824c1409124a60e63c3a7ff3278a4dc5fa8

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Merge "(feat)n1sdp: add support for OP-TEE SPMC" into integration

(feat)n1sdp: add support for OP-TEE SPMC

These changes are to add support for loading and booting
OP-TEE as SPMC running at SEL1 for N1SDP platform.

Signed-off-by: Vishnu Banavath <vishnu.banavath@

(feat)n1sdp: add support for OP-TEE SPMC

These changes are to add support for loading and booting
OP-TEE as SPMC running at SEL1 for N1SDP platform.

Signed-off-by: Vishnu Banavath <vishnu.banavath@arm.com>
Change-Id: I0514db646d4868b6f0c56f1ea60495cb3f7364fd

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Merge "feat(tc): introduce TC2 platform" into integration