| 3aa8fa77 | 16-Aug-2022 |
Harrison Mutai <harrison.mutai@arm.com> |
build: fix semantic ver generation for windows
Fix syntax error when generating semantic versions on windows hosts.
Change-Id: Idba8827145b829a8ba07ff0540407dbfa1ca7984 Signed-off-by: Harrison Muta
build: fix semantic ver generation for windows
Fix syntax error when generating semantic versions on windows hosts.
Change-Id: Idba8827145b829a8ba07ff0540407dbfa1ca7984 Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
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| 0e6977ee | 19-Jan-2022 |
Jens Wiklander <jens.wiklander@linaro.org> |
feat(qemu): increase size of bl31
Increases the SRAM to a full 1MB and also increase BL31 size to have room to spare for debugging.
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org> Change-
feat(qemu): increase size of bl31
Increases the SRAM to a full 1MB and also increase BL31 size to have room to spare for debugging.
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org> Change-Id: I584f9d409a1f653a3dfc7cf2b95706ada367c70e
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| 958b8396 | 16-Aug-2022 |
Julius Werner <jwerner@chromium.org> |
Merge "refactor(bl31): introduce vendor extend rodata section" into integration |
| a36af977 | 15-Aug-2022 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge changes from topic "st-clk-cleanup" into integration
* changes: refactor(st-clock): code size optimization refactor(st-clock): remove unused PLL field |
| b48cd784 | 09-Aug-2022 |
Pali Rohár <pali@kernel.org> |
docs(marvell): document UART image downloading
For A3K there are two different tools for booting Armada37x0 platform over UART, one from Marvell and second from CZ.NIC. For A8K there is just one my
docs(marvell): document UART image downloading
For A3K there are two different tools for booting Armada37x0 platform over UART, one from Marvell and second from CZ.NIC. For A8K there is just one my own mvebu64boot tool.
Add documentation how to build these tools and how to download TF-A image over UART to boot TF-A without flashing it to non-volatile storage.
Signed-off-by: Pali Rohár <pali@kernel.org> Change-Id: Ifa03584010a9c40496a34e6d5b9f3b78cb2cc89b
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| 6a502227 | 11-Aug-2022 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "fix(errata): workaround for Neoverse-V1 erratum 1618635" into integration |
| 53be5274 | 11-Aug-2022 |
Joanna Farley <joanna.farley@arm.com> |
Merge "fix(build): discard sections also with SEPARATE_NOBITS_REGION" into integration |
| 5d75d715 | 11-Aug-2022 |
Bipin Ravi <bipin.ravi@arm.com> |
Merge "fix(build): disable default PIE when linking" into integration |
| 8f23476e | 11-Aug-2022 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "feat(bl): add interface to query TF-A semantic ver" into integration |
| 64207f85 | 09-Apr-2022 |
Samuel Holland <samuel@sholland.org> |
fix(build): discard sections also with SEPARATE_NOBITS_REGION
Some linker sections are discarded since 511046eaa28f ("BL31: discard .dynsym .dynstr .hash sections to make ENABLE_PIE work"). However,
fix(build): discard sections also with SEPARATE_NOBITS_REGION
Some linker sections are discarded since 511046eaa28f ("BL31: discard .dynsym .dynstr .hash sections to make ENABLE_PIE work"). However, that logic was placed inside a preprocessor condition, so it only applied to the !SEPARATE_NOBITS_REGION case. Move the /DISCARD/ block down so it applies in all cases.
Signed-off-by: Samuel Holland <samuel@sholland.org> Change-Id: I6604609f2321a2a9c32a25721a697c320108a974
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| 7b592418 | 09-Apr-2022 |
Samuel Holland <samuel@sholland.org> |
fix(build): disable default PIE when linking
Commit f7ec31db2d ("Disable PIE compilation option") allowed building a non-relocatable firmware with a default-PIE toolchain by disabling PIE at compila
fix(build): disable default PIE when linking
Commit f7ec31db2d ("Disable PIE compilation option") allowed building a non-relocatable firmware with a default-PIE toolchain by disabling PIE at compilation time. This prevents the compiler from generating relocations against a GOT.
However, when a default-PIE GCC is used as the linker, the final binary will still be a PIE, containing an (unused) GOT and dynamic symbol table. These structures do not affect execution, but they waste space in the firmware binary. Disable PIE at link time to recover this space.
Change-Id: I2be7ac9c1a957f6db8d75efe6e601e9a5760a925 Signed-off-by: Samuel Holland <samuel@sholland.org>
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| f924258d | 10-Aug-2022 |
Bipin Ravi <bipin.ravi@arm.com> |
Merge "fix(bl31): pass the EA bit to 'delegate_sync_ea'" into integration |
| 33223c3a | 29-Mar-2022 |
Yann Gautier <yann.gautier@foss.st.com> |
refactor(stm32mp15-fdts): remove ETZPC status
The ETZPC is always secure, and the driver does no more rely on secure-status (and status) DT property. Remove them from the SoC DT file.
Signed-off-by
refactor(stm32mp15-fdts): remove ETZPC status
The ETZPC is always secure, and the driver does no more rely on secure-status (and status) DT property. Remove them from the SoC DT file.
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com> Change-Id: I5f1d3534679553d79e6866396cd70e21a595ef6a
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| e9ff3486 | 29-Mar-2022 |
Yann Gautier <yann.gautier@foss.st.com> |
refactor(st-drivers): do not rely on DT in etzpc_init
The ETZPC peripheral is always secure, and has a fixed address, given by STM32MP1_ETZPC_BASE. This is then not needed to check that in DT.
Sign
refactor(st-drivers): do not rely on DT in etzpc_init
The ETZPC peripheral is always secure, and has a fixed address, given by STM32MP1_ETZPC_BASE. This is then not needed to check that in DT.
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com> Change-Id: Ifb0779abaf830e1e5a469c72181c2b2726fb47b5
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| 3ff1ff40 | 21-Jun-2022 |
Gabriel Fernandez <gabriel.fernandez@foss.st.com> |
refactor(st-clock): code size optimization
Clock name is not used and can be removed for code size optimization.
Change-Id: I75f6a1828e4374004e31a7ce13fa6885c52bbac3 Signed-off-by: Gabriel Fernande
refactor(st-clock): code size optimization
Clock name is not used and can be removed for code size optimization.
Change-Id: I75f6a1828e4374004e31a7ce13fa6885c52bbac3 Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
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| b44f5acf | 14-Feb-2022 |
Gabriel Fernandez <gabriel.fernandez@foss.st.com> |
refactor(st-clock): remove unused PLL field
The divn_max field is unused, remove it.
Change-Id: I971912bcc035f16963d98dfa88782c8aed4415f2 Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st
refactor(st-clock): remove unused PLL field
The divn_max field is unused, remove it.
Change-Id: I971912bcc035f16963d98dfa88782c8aed4415f2 Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
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| 1631f9c7 | 09-Aug-2022 |
Olivier Deprez <olivier.deprez@arm.com> |
Merge "feat(sve): support full SVE vector length" into integration |
| 8a68e864 | 05-Aug-2022 |
Leon Chen <leon.chen@mediatek.com> |
refactor(bl31): introduce vendor extend rodata section
The purpose of including vendor extend plat.ld.rodata.inc linker script is for compactly collecting vendor rodata in intrinsic rodata section.
refactor(bl31): introduce vendor extend rodata section
The purpose of including vendor extend plat.ld.rodata.inc linker script is for compactly collecting vendor rodata in intrinsic rodata section. If vendors define a standalone section and assign the section placed after __RW_END__, the raw bindry(bl31.bin) will include bss section with zero value and increase binary size.
Signed-off-by: Leon Chen <leon.chen@mediatek.com> Change-Id: I46dd8b02bfb26af1dcca27f61b3ea29ca74bbbd6
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| 4a0d8632 | 08-Aug-2022 |
Joanna Farley <joanna.farley@arm.com> |
Merge "docs(juno): fix broken link" into integration |
| 89e4cea1 | 24-Jun-2022 |
Arthur She <arthur.she@linaro.org> |
docs(juno): fix broken link
The URL of the Juno Getting Started Guide has been changed. Fix the broken link.
Signed-off-by: Arthur She <arthur.she@linaro.org> Change-Id: I55697f2f1f787c32d1ea7dfcf9
docs(juno): fix broken link
The URL of the Juno Getting Started Guide has been changed. Fix the broken link.
Signed-off-by: Arthur She <arthur.she@linaro.org> Change-Id: I55697f2f1f787c32d1ea7dfcf9eda619906cdb5d
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| 000e25bf | 07-Aug-2022 |
Joanna Farley <joanna.farley@arm.com> |
Merge "fix(versal): use only one space for indentation" into integration |
| 0da574c1 | 07-Aug-2022 |
Joanna Farley <joanna.farley@arm.com> |
Merge changes from topic "xilinx-versal-coding-style" into integration
* changes: fix(versal): fix code indentation issues fix(versal): fix macro coding style issues |
| 14a6fed5 | 28-Feb-2022 |
Juan Pablo Conde <juanpablo.conde@arm.com> |
fix(errata): workaround for Neoverse-V1 erratum 1618635
Neoverse-V1 erratum 1618635 is a Cat B erratum that applies to revision r0p0. It is fixed in r1p0. The workaround is done through the instruct
fix(errata): workaround for Neoverse-V1 erratum 1618635
Neoverse-V1 erratum 1618635 is a Cat B erratum that applies to revision r0p0. It is fixed in r1p0. The workaround is done through the instruction patching mechanism, which is performed by a write sequence of IMPLEMENTATION DEFINED registers.
SDEN can be found here: https://developer.arm.com/documentation/SDEN1401781/latest/
Signed-off-by: Juan Pablo Conde <juanpablo.conde@arm.com> Change-Id: I53e406735cd3a2a930fdc72ebce3bbed97100168
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| 4d879e1e | 02-Aug-2022 |
Jamie Fox <jamie.fox@arm.com> |
fix(lib/psa): update measured boot handle
When the measured boot service was upstreamed to TF-M, its static handle was reallocated into the user partitions range. This change updates the static hand
fix(lib/psa): update measured boot handle
When the measured boot service was upstreamed to TF-M, its static handle was reallocated into the user partitions range. This change updates the static handle here to make the service accessible.
Also removes the SIDs and Versions, since they are unused when a service is accessed through a stateless handle, which encodes both service ID and version. The attestation and measured boot services only support access through their handles.
Signed-off-by: Jamie Fox <jamie.fox@arm.com> Change-Id: I9d2ff1aad19470728289d574be3d5d11bdabeef4
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| 73b73b1a | 04-Aug-2022 |
Lauren Wehrmeister <lauren.wehrmeister@arm.com> |
Merge "fix: make TF-A use provided OpenSSL binary" into integration |