feat(stm32mp1): manage second NAND OTP on STM32MP13

On STM32MP13, 2 OTP fuses can be used to configure NAND devices.
By default OTP CFG9 is used for sNAND. A new OTP (CFG10) is used
to configure raw

feat(stm32mp1): manage second NAND OTP on STM32MP13

On STM32MP13, 2 OTP fuses can be used to configure NAND devices.
By default OTP CFG9 is used for sNAND. A new OTP (CFG10) is used
to configure raw NAND. Thanks to bit 0 of CFG10 OTP, this default
configuration can be switched.
For sNAND on STM32MP13, the NAND_PARAM_STORED_IN_OTP is not used.
The sNAND parameters have to be taken from OTP bits.

Change-Id: Ib95e0f9b9e66179a58b07f723ea01dce68b96475
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>

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feat(stm32mp1): add define for external scratch buffer for nand devices

Override the default platform function to use an external buffer
on STM32MP13 platform.
It allows to use a temporary buffer lo

feat(stm32mp1): add define for external scratch buffer for nand devices

Override the default platform function to use an external buffer
on STM32MP13 platform.
It allows to use a temporary buffer located at the SRAM1 memory end.

Signed-off-by: Lionel Debieve <lionel.debieve@foss.st.com>
Change-Id: Ibd84bb336c60af24608268916b3a18bb5a0fa3db

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feat(mtd): add platform function to allow using external buffer

The scratch buffer could be large. The new function allows
platform to defined its own external buffer or use the default
one.

Signed

feat(mtd): add platform function to allow using external buffer

The scratch buffer could be large. The new function allows
platform to defined its own external buffer or use the default
one.

Signed-off-by: Lionel Debieve <lionel.debieve@foss.st.com>
Change-Id: Ib7ab8ff19fa0a9cb06e364f058b91af58c3c471a

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feat(libc): introduce __maybe_unused

Checkpatch script doesn't support __unused macro. To avoid errors, add
__maybe_unused macro, which is supported.

Signed-off-by: Yann Gautier <yann.gautier@st.co

feat(libc): introduce __maybe_unused

Checkpatch script doesn't support __unused macro. To avoid errors, add
__maybe_unused macro, which is supported.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I795134fb152991f2bc804a6b3be2fd1da7032758

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Merge changes I60b3b59e,Ibd5d22b4 into integration

* changes:
fix(ufs): init utrlba/utrlbau with desc_base
fix(ufs): fix slot base address computation

refactor(stm32mp15-fdts): remove timers15 node

The node is currently not used in TF-A. Remove it.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: Iedc4745f155ebb9c80132311a8623e4498f06

refactor(stm32mp15-fdts): remove timers15 node

The node is currently not used in TF-A. Remove it.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: Iedc4745f155ebb9c80132311a8623e4498f0689f

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refactor(stm32mp15-fdts): remove unused secure-status properties

For peripheral where both status and secure-status are set to okay,
the function fdt_get_status() returns the same status (DT_SHARED)

refactor(stm32mp15-fdts): remove unused secure-status properties

For peripheral where both status and secure-status are set to okay,
the function fdt_get_status() returns the same status (DT_SHARED) if
secure-status property is omitted. This secure-status property can then
be removed in boards DT files for iwdg nodes.

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: I9f9360842d4d41288db0cf1b92063f347c72d137

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refactor(stm32mp15-fdts): remove RCC secure-status

The RCC security is managed with a dedicated compatible:
"st,stm32mp1-rcc-secure" [1].
Remove useless secure-status property in boards rcc nodes.

refactor(stm32mp15-fdts): remove RCC secure-status

The RCC security is managed with a dedicated compatible:
"st,stm32mp1-rcc-secure" [1].
Remove useless secure-status property in boards rcc nodes.

[1] 812daf916c ("feat(st): update the security based on new compatible")

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: Iff31044ade78dd9c432120dce65375fe2b0d36d6

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Merge "feat(stm32mp15-fdts): add Avenger96 board with STM32MP157A DHCOR SoM" into integration

feat(stm32mp15-fdts): add Avenger96 board with STM32MP157A DHCOR SoM

This should replace the stm32mp157a-avenger96.dts with the new device
tree files split into the STM32MP15 DHCOR SoM definition an

feat(stm32mp15-fdts): add Avenger96 board with STM32MP157A DHCOR SoM

This should replace the stm32mp157a-avenger96.dts with the new device
tree files split into the STM32MP15 DHCOR SoM definition and the
Avenger96 baseboard like it's done in Linux and U-Boot.

Differences to stm32mp157a-avenger96.dts:
- Enable sdmmc2 for booting from eMMC
- improved clock settings like in U-Boot commit b6055945
"ARM: dts: stm32: Adjust PLL4 settings on AV96 again"
- improved DDR settings for DHSOMs like in U-Boot commit 92ca0f74
"ARM: dts: stm32: Synchronize DDR setttings on DH SoMs"

TF-A with this new dts(i) files on this board was fully tested with
the latest OP-TEE developer setup.

Change-Id: I85ce8eca7747965af3555fc19fd7b192dc3e5740
Signed-off-by: Johann Neuhauser <jneuhauser@dh-electronics.com>

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Merge changes from topic "ffa_el3_spmc" into integration

* changes:
feat(tsp): enable test cases for EL3 SPMC
feat(tsp): increase stack size for tsp
feat(tsp): add ffa_helpers to enable more F

Merge changes from topic "ffa_el3_spmc" into integration

* changes:
feat(tsp): enable test cases for EL3 SPMC
feat(tsp): increase stack size for tsp
feat(tsp): add ffa_helpers to enable more FF-A functionality

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feat(tsp): enable test cases for EL3 SPMC

Introduce initial test cases to the TSP which are
designed to be exercised by the FF-A Test Driver
in the Normal World. These have been designed to
test bas

feat(tsp): enable test cases for EL3 SPMC

Introduce initial test cases to the TSP which are
designed to be exercised by the FF-A Test Driver
in the Normal World. These have been designed to
test basic functionality of the EL3 SPMC.

These tests currently ensure the following functionality:
- Partition discovery.
- Direct messaging.
- Communication with a Logical SP.
- Memory Sharing and Lending ABIs
- Sharing of contiguous and non-contiguous memory regions.
- Memory region descriptors spread of over multiple
invocations.

Signed-off-by: Marc Bonnici <marc.bonnici@arm.com>
Signed-off-by: Shruti Gupta <shruti.gupta@arm.com>
Change-Id: Iaee4180aa18d6b7ac7b53685c6589f0ab306e876

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feat(tsp): increase stack size for tsp

TSP testcases for EL3 SPMC have higher stack usage.

Change-Id: Ib5bfdccc6d0f65174e257f3b0e8b41bcd3c704a6
Signed-off-by: Shruti Gupta <shruti.gupta@arm.com>

feat(tsp): add ffa_helpers to enable more FF-A functionality

Include ffa_helpers originally taken from the TF-A Tests repo
to provide support for additional FF-A functionality.

Change-Id: Iacc3ee27

feat(tsp): add ffa_helpers to enable more FF-A functionality

Include ffa_helpers originally taken from the TF-A Tests repo
to provide support for additional FF-A functionality.

Change-Id: Iacc3ee270d5e3903f86f8078ed915d1e791c1298
Signed-off-by: Marc Bonnici <marc.bonnici@arm.com>
Signed-off-by: Shruti Gupta <shruti.gupta@arm.com>

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fix(gpt): correct the GPC enable sequence

Since GPC control register fields are permitted to be cached in a TLB,
invalidate TLB after setting fields to ensure future checks are using
the updated val

fix(gpt): correct the GPC enable sequence

Since GPC control register fields are permitted to be cached in a TLB,
invalidate TLB after setting fields to ensure future checks are using
the updated values.

Signed-off-by: Kathleen Capella <kathleen.capella@arm.com>
Change-Id: I95630b40b673363bbf74da2705deca03089fff3a

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Merge "fix(errata): workaround for Cortex-A510 erratum 2371937" into integration

Merge "fix(errata): workaround for Cortex-A78C erratum 2395411" into integration

fix(errata): workaround for Cortex-A78C erratum 2395411

Cortex-A78C erratum 2395411 is a Cat B erratum that affects
revisions r0p1 and r0p2, and is currently open. The workaround
is to set CPUACTLR2

fix(errata): workaround for Cortex-A78C erratum 2395411

Cortex-A78C erratum 2395411 is a Cat B erratum that affects
revisions r0p1 and r0p2, and is currently open. The workaround
is to set CPUACTLR2_EL1[40] to 1, which will disable folding
of demand requests into older prefetches with L2 miss requests
outstanding.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN2004089/latest

Signed-off-by: Akram Ahmad <Akram.Ahmad@arm.com>
Change-Id: I4f0fb278ac20a2eb4dd7e4efd1b1246dd85e48c4

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Merge "fix(errata): workaround for Cortex-A710 erratum 2147715" into integration

fix(errata): workaround for Cortex-A510 erratum 2371937

Cortex-A510 erratum 2371937 is a Cat B erratum that applies
to revisions r0p0, r0p1, r0p2, r0p3, r1p0, and r1p1. It is
fixed in r1p2. The work

fix(errata): workaround for Cortex-A510 erratum 2371937

Cortex-A510 erratum 2371937 is a Cat B erratum that applies
to revisions r0p0, r0p1, r0p2, r0p3, r1p0, and r1p1. It is
fixed in r1p2. The workaround is to set the ATOM field of
CPUECTLR_EL1 (bits [40:38]) to 0b010, which will force all
cacheable atomic operations to be executed near.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN1873351/latest
https://developer.arm.com/documentation/SDEN1873361/latest

Signed-off-by: Akram Ahmad <Akram.Ahmad@arm.com>
Change-Id: Ia219a609a3397e39631de65831ecff8a3cd1227e

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Merge changes from topic "ffa_el3_spmc" into integration

* changes:
feat(tsp): add FF-A support to the TSP
feat(fvp/tsp_manifest): add example manifest for TSP
fix(spmc): fix relinquish valida

Merge changes from topic "ffa_el3_spmc" into integration

* changes:
feat(tsp): add FF-A support to the TSP
feat(fvp/tsp_manifest): add example manifest for TSP
fix(spmc): fix relinquish validation check

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feat(tsp): add FF-A support to the TSP

This patch adds the FF-A programming model in the test
secure payload to ensure that it can be used to test
the following spec features.

1. SP initialisation

feat(tsp): add FF-A support to the TSP

This patch adds the FF-A programming model in the test
secure payload to ensure that it can be used to test
the following spec features.

1. SP initialisation on the primary and secondary cpus.
2. An event loop to receive direct requests and respond
with direct responses.
3. Ability to receive messages that indicate power on
and off of a cpu.
4. Ability to handle a secure interrupt.

Signed-off-by: Achin Gupta <achin.gupta@arm.com>
Signed-off-by: Marc Bonnici <marc.bonnici@arm.com>
Signed-off-by: Shruti <shruti.gupta@arm.com>
Change-Id: I81cf744904d5cdc0b27862b5e4bc6f2cfe58a13a

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Merge "feat(qemu): increase size of bl31" into integration

Merge "build: fix syntax error in semantic ver generation" into integration

build: fix syntax error in semantic ver generation

Change-Id: I344aa5c779ec3f0a410d3b8bc42b6014a9b37314
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>