feat(libfdt): upgrade libfdt source files

Update the libfdt source files to the upstream commit e37c256 [1].

[1] https://github.com/dgibson/dtc/commit/e37c256

Change-Id: I00e29b467ff6f8c094f682452

feat(libfdt): upgrade libfdt source files

Update the libfdt source files to the upstream commit e37c256 [1].

[1] https://github.com/dgibson/dtc/commit/e37c256

Change-Id: I00e29b467ff6f8c094f68245232a7cedeaa14aef
Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>

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docs(prerequisites): upgrade to Mbed TLS 2.28.1

In anticpation of the next Trusted Firmware release update the to newest
2.x Mbed TLS library [1].

Note that the Mbed TLS project published version 3

docs(prerequisites): upgrade to Mbed TLS 2.28.1

In anticpation of the next Trusted Firmware release update the to newest
2.x Mbed TLS library [1].

Note that the Mbed TLS project published version 3.x some time ago.
However, as this is a major release with API breakages, upgrading to
this one might require some more involved changes in TF-A, which we are
not ready to do. We shall upgrade to Mbed TLS 3.x after the v2.8 release
of TF-A.

[1] https://github.com/Mbed-TLS/mbedtls/tree/v2.28.1

Change-Id: I7594ad062a693d2ecc3b1705e944dce2c3c43bb2
Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>

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Merge "feat(fvp): build delegated attestation in BL31" into integration

feat(rdn2): enable extended SPI support

Enable the GIC_EXT_INTID configuration to support extended interrupt
IDs for RD-N2 multichip platform.

Signed-off-by: Vivek Gautam <vivek.gautam@arm.com>
Cha

feat(rdn2): enable extended SPI support

Enable the GIC_EXT_INTID configuration to support extended interrupt
IDs for RD-N2 multichip platform.

Signed-off-by: Vivek Gautam <vivek.gautam@arm.com>
Change-Id: Ic8d59ba0e692e5f13f3cdeffc64d76cd4741aa11

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feat(rdn2): add SPI ID ranges for RD-N2 multichip platform

Add the SPI ID ranges for various chips on RD-N2 multichip platform
(rdn2cfg2). Also fix the max SPI ID for chip#0 that was incorrectly
set

feat(rdn2): add SPI ID ranges for RD-N2 multichip platform

Add the SPI ID ranges for various chips on RD-N2 multichip platform
(rdn2cfg2). Also fix the max SPI ID for chip#0 that was incorrectly
set.
The SPI ranges for rdn2cfg2 platform are as shown below:
============================================
Chip# | CHIP_START_INTID | CHIP_END_INTID
============================================
0 | 32 | 511
1 | 512 | 991
2 | 4096 | 4575
3 | 4576 | 5055

Signed-off-by: Vivek Gautam <vivek.gautam@arm.com>
Change-Id: I146944af1ffe52c300eef2ef48b1077a9559bf41

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Merge "chore(rpi3): remove redundant code" into integration

Merge "docs(maintainers): add NPU driver owners" into integration

docs(maintainers): add NPU driver owners

Code owners have been added for the Arm(R) Ethos(TM)-N NPU driver.

Change-Id: I0bda0d95151cdff5cd3a793c6c0e9ef6a9a5f50b
Signed-off-by: Mikael Olsson <mikael

docs(maintainers): add NPU driver owners

Code owners have been added for the Arm(R) Ethos(TM)-N NPU driver.

Change-Id: I0bda0d95151cdff5cd3a793c6c0e9ef6a9a5f50b
Signed-off-by: Mikael Olsson <mikael.olsson@arm.com>

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Merge "fix(versal_net): Enable a78 errata workarounds" into integration

fix(versal_net): Enable a78 errata workarounds

TF-A is reporting that erratum are missing to be enabled.

Enable the Following errata workaround to Cortex-A78 AE CPU for versal_net
ERRATA_A78_AE_194

fix(versal_net): Enable a78 errata workarounds

TF-A is reporting that erratum are missing to be enabled.

Enable the Following errata workaround to Cortex-A78 AE CPU for versal_net
ERRATA_A78_AE_1941500
ERRATA_A78_AE_1951502
ERRATA_A78_AE_2376748
ERRATA_A78_AE_2395408

For further information refer to
https://developer.arm.com/documentation/SDEN1707912/1300/

Signed-off-by: Akshay Belsare <Akshay.Belsare@amd.com>
Change-Id: Ib7fc16e035feab1dfbd88c1f8ce128b057eee86d

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fix(cpus): workaround for Cortex-A510 erratum 2666669

Cortex-A510 erratum 2666669 applies to revisions r1p1 and lower,
and is fixed in r1p2. The errata is mitigated by setting
IMP_CPUACTLR_EL1[38] t

fix(cpus): workaround for Cortex-A510 erratum 2666669

Cortex-A510 erratum 2666669 applies to revisions r1p1 and lower,
and is fixed in r1p2. The errata is mitigated by setting
IMP_CPUACTLR_EL1[38] to 1.

SDEN documentation:
https://developer.arm.com/documentation/SDEN1873351/latest
https://developer.arm.com/documentation/SDEN1873361/latest

Signed-off-by: Akram Ahmad <Akram.Ahmad@arm.com>
Change-Id: Ief27e4a155e43e75f05f2710d0c7bd5da2dec43f

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feat(fvp): build delegated attestation in BL31

Right now, the delegated attestation module is not used in TF-A. This
means it's not even getting built and so the CI system cannot detect
build regres

feat(fvp): build delegated attestation in BL31

Right now, the delegated attestation module is not used in TF-A. This
means it's not even getting built and so the CI system cannot detect
build regressions.

Eventually, delegated attestation will be involved in a new runtime
service exposed by BL31 to lower exception levels. We are not there
yet but let's already include it into BL31 image, so we get build
coverage and static analysis on the code. Note that we make sure to
cover both PLAT_RSS_NOT_SUPPORTED=0 and PLAT_RSS_NOT_SUPPORTED=1
configurations.

Delegated attestation is currently made dependent on measured boot
support. This dependency is not at the source code level (attestation
code does not invoke any measured boot interfaces) but it is rather a
logical dependency: attestation without boot measurements is not very
useful...

For now, this is good enough for our purpose but the conditions under
which the attestation code is included might change in the future.

Change-Id: I616715c3dd0418a1bbf1019df3ff9acd8461e705
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>

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fix(sme): add missing ISBs

EL3 is configured to trap accesses to SME registers (via
CPTR_EL3.ESM=0). To allow SME instructions, this needs to be temporarily
disabled before changing system registers

fix(sme): add missing ISBs

EL3 is configured to trap accesses to SME registers (via
CPTR_EL3.ESM=0). To allow SME instructions, this needs to be temporarily
disabled before changing system registers. If the PE delays the effects
of writes to system registers then accessing the SME registers will trap
without an isb. This patch adds the isb to restore functionality.

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: I8ee5ecaec978dde2525631daa682a182ad8f7f04

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Merge "fix(versal): enable a72 erratum 859971 and 1319367" into integration

fix(versal): enable a72 erratum 859971 and 1319367

TF-A is reporting that above two erratum are missing to be enabled that's
why enable them by default.

For futher information please refer to
https

fix(versal): enable a72 erratum 859971 and 1319367

TF-A is reporting that above two erratum are missing to be enabled that's
why enable them by default.

For futher information please refer to
https://developer.arm.com/documentation/epm012079/11/

where
859971 is "Speculative instruction prefetch to Execute-never (XN) memory
could cause deadlock or data integrity issue" and
1319367 is "Speculative AT instruction using out-of-context translation
regime could cause subsequent request to generate an incorrect
translation".

Change-Id: I408706713a169e53db63ac5657751b0b003e646d
Signed-off-by: Michal Simek <michal.simek@amd.com>

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Merge "fix(ufs): retry commands on unit attention" into integration

Merge "fix(sptool): operators "is/is not" in sp_mk_gen.py" into integration

Merge "fix(mt8186): fix EMI_MPU domain setting for DSP" into integration

Merge "fix: backtrace stack unwind misses lr adjustment" into integration

Merge "fix(rk3399): explicitly define the sys_sleep_flag_sram type" into integration

chore(rpi3): remove redundant code

The pwr_domain_pwr_down_wfi entry is overridden by a newer
implementation. This removes the last reference to
rpi3_pwr_domain_pwr_down_wfi. Remove both as they are

chore(rpi3): remove redundant code

The pwr_domain_pwr_down_wfi entry is overridden by a newer
implementation. This removes the last reference to
rpi3_pwr_domain_pwr_down_wfi. Remove both as they are not needed

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: Ie65c40935cd1ed3c673ffdc9aa72064f5ab4032e

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fix(rk3399): explicitly define the sys_sleep_flag_sram type

Recent GCC versions now do array-bounds checking which fails for
sys_sleep_flag_sram because the struct is larger than the 8-bytes
size th

fix(rk3399): explicitly define the sys_sleep_flag_sram type

Recent GCC versions now do array-bounds checking which fails for
sys_sleep_flag_sram because the struct is larger than the 8-bytes
size that (void *) is

This variable is only used in one place as the struct,
so it can be defined with the struct type.

Resolves:
plat/rockchip/px30/drivers/pmu/pmu.c: In function 'rockchip_soc_sys_pwr_dm_suspend':
plat/rockchip/px30/drivers/pmu/pmu.c:977:23: error: array subscript 'struct psram_data_t[0]' is partly outside array bounds of 'void[8]' [-Werror=array-bounds]
977 | psram_boot_cfg->pm_flag &= ~PM_WARM_BOOT_BIT;

Change-Id: Ifbe42d11d0c7875f6cb23dc0b7ffb3f3f90c55a8
Signed-off-by: Scott Parlane <scott@parlanenz.com>

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Merge changes from topic "fvp_dts_rework" into integration

* changes:
fix(fvp_ve): fdts: Fix vexpress,config-bus subnode names
fix(fvp): fdts: Fix idle-states entry method
fix(fvp): fdts: fix

Merge changes from topic "fvp_dts_rework" into integration

* changes:
fix(fvp_ve): fdts: Fix vexpress,config-bus subnode names
fix(fvp): fdts: Fix idle-states entry method
fix(fvp): fdts: fix memtimer subframe addressing
feat(fvp): fdts: update rtsm_ve DT files from the Linux kernel
refactor(fvp): fdts: consolidate GICv2 base FVP DT files
refactor(fvp): fdts: consolidate GICv3 base FVP DT files
feat(fvp): dts: drop 32-bit .dts files
refactor(fvp): fdts: merge motherboard .dtsi files
refactor(fvp_ve): fdts: prepare Cortex-A5 and A7 model DTs
fix(fvp): fdts: unify and fix PSCI nodes

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fix(gicv3/multichip): fix overflow caused by left shift

When spi_id_max is 5119, the expression `(spi_id_max - 4096U + 1U >> 5)`
evaluates to 32 leading to undefined behavior when using it to left
s

fix(gicv3/multichip): fix overflow caused by left shift

When spi_id_max is 5119, the expression `(spi_id_max - 4096U + 1U >> 5)`
evaluates to 32 leading to undefined behavior when using it to left
shift 1. Fix this undefined behavior.

Reported-by coverity scan:
https://lists.trustedfirmware.org/archives/list/tf-a@lists.trustedfirmware.org/thread/RMB4U7COL6IONZWEGF2FWXOQ6FPDIT4U/

```
large_shift: In expression 1 << (spi_id_max - 4096U + 1U >> 5), left
shifting by more than 31 bits has undefined behavior. The shift
amount, spi_id_max - 4096U + 1U >> 5, is as much as 32.
```

Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
Change-Id: I5e77a78b81a6d0367875e7ea432a82b6ba0e587c

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Merge "feat(cpu): add library support for Hunter ELP" into integration