build: deprecate Arm rdn1edge and sgi575 FVP platforms

Arm has decided to deprecate the sgi575 and rdn1edge platforms.
The development of software and fast models for these platforms
has been discon

build: deprecate Arm rdn1edge and sgi575 FVP platforms

Arm has decided to deprecate the sgi575 and rdn1edge platforms.
The development of software and fast models for these platforms
has been discontinued. rdn1edge platform has been superseded by the
rdn2 platform, which is already supported in TF-A and CI work is
underway for this platform.

Change-Id: If2228fb73549b244c3a5b0e5746617b3f24fe771
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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feat(imx8mm): add BL31 PIE support

Enable PIE support so the BL31 firmware can be loaded from anywhere
within the OCRAM (SRAM). For the PIE support we only need to replace the
BL31_BASE define by th

feat(imx8mm): add BL31 PIE support

Enable PIE support so the BL31 firmware can be loaded from anywhere
within the OCRAM (SRAM). For the PIE support we only need to replace the
BL31_BASE define by the BL31_START symbol which is a relocatable and we
need to enable it by setting ENABLE_PIE := 1.

Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
Change-Id: I52e654917167f0faf6aa437da233d8faf1f2bb26

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refactor(imx8mm): introduce BL2_SIZE and BL31_SIZE

No functional change.

Introduce BLx_SIZE defines and calculate the limits based on the
BLx_BASE and the BLx_SIZE define. Also make use of SZ_128K

refactor(imx8mm): introduce BL2_SIZE and BL31_SIZE

No functional change.

Introduce BLx_SIZE defines and calculate the limits based on the
BLx_BASE and the BLx_SIZE define. Also make use of SZ_128K to make it
easier to read. This is required for later BL31 PIE support since it
drops the calculation based on the BL31_LIMIT and BL31_BASE.

Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
Change-Id: I8670faa5d5a572ef230011594f3d0d594fb257d9

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refactor(imx8mm): make use of setup_page_tables()

No functional change. Use the setup_page_tables() helper function which
does the three calls for us. Also the function has some logging support
whic

refactor(imx8mm): make use of setup_page_tables()

No functional change. Use the setup_page_tables() helper function which
does the three calls for us. Also the function has some logging support
which will be nice during debugging.

Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
Change-Id: Ic465491ff5468e812e805de56be3b6b92d245080

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refactor(imx8mm): cleanup the mmap region settings

No functional change.

Introduce the bl_regions array to gather all regions and make use of the
MAP_REGION_FLAT() macro. The array is than passed t

refactor(imx8mm): cleanup the mmap region settings

No functional change.

Introduce the bl_regions array to gather all regions and make use of the
MAP_REGION_FLAT() macro. The array is than passed to mmap_add() to map
all regions. While on it introduce some defines so the addr, size and
flags can be read more easily.

Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
Change-Id: I9f0ae9fc89514db71bef734b867c46574833831c

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feat(imx8mn): add BL31 PIE support

Enable PIE support so the BL31 firmware can be loaded from anywhere
within the OCRAM (SRAM). For the PIE support we only need to replace the
BL31_BASE define by th

feat(imx8mn): add BL31 PIE support

Enable PIE support so the BL31 firmware can be loaded from anywhere
within the OCRAM (SRAM). For the PIE support we only need to replace the
BL31_BASE define by the BL31_START symbol which is a relocatable and we
need to enable it by setting ENABLE_PIE := 1.

Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
Change-Id: I33c8e35c35112d70d2725eebe484a853a8aad9e0

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refactor(imx8mn): introduce BL31_SIZE

Introduce BL31_SIZE define and calculate the limit based on the
BL31_BASE and the BL31_SIZE define. Also make use of SZ_128K to make it
easier to read. This is

refactor(imx8mn): introduce BL31_SIZE

Introduce BL31_SIZE define and calculate the limit based on the
BL31_BASE and the BL31_SIZE define. Also make use of SZ_128K to make it
easier to read. This is required for later BL31 PIE support since it
drops the calculation based on the BL31_LIMIT and BL31_BASE.

While on it remove the duplicated <lib/utils_def.h> include.

Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
Change-Id: Ifca40bd5682ef993db986439115abd9e9a66a5b2

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refactor(imx8mn): make use of setup_page_tables()

No functional change.

Use the setup_page_tables() helper function which does the three calls
for us. Also the function has some logging support whi

refactor(imx8mn): make use of setup_page_tables()

No functional change.

Use the setup_page_tables() helper function which does the three calls
for us. Also the function has some logging support which will be nice
during debugging.

Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
Change-Id: I2f0182f19300a3a57bbeb7e2107c5fb5525dd0c1

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refactor(imx8mn): cleanup the mmap region settings

No functional change.

Introduce the bl_regions array to gather all regions and make use of the
MAP_REGION_FLAT() macro. The array is than passed t

refactor(imx8mn): cleanup the mmap region settings

No functional change.

Introduce the bl_regions array to gather all regions and make use of the
MAP_REGION_FLAT() macro. The array is than passed to mmap_add() to map
all regions. While on it introduce some defines so the addr, size and
flags can be read more easily.

Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
Change-Id: Id5849d2a7326a943927f458f1c6abbc041f5be18

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feat(imx8mp): add BL31 PIE support

Enable PIE support so the BL31 firmware can be loaded from anywhere
within the OCRAM (SRAM). How important this is shows the back and forth
of the BL31_BASE addres

feat(imx8mp): add BL31 PIE support

Enable PIE support so the BL31 firmware can be loaded from anywhere
within the OCRAM (SRAM). How important this is shows the back and forth
of the BL31_BASE address starting with TF-A v2.5. Since then the
BL31_BASE address wasn't stable and choosing the correct combination of
SPL version loadaddress and TF-A version loadaddr was tricky.

For the PIE support we only need to replace the BL31_BASE by the
BL31_START which is a relocatable symbol and to enable it by setting
ENABLE_PIE := 1.

Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
Change-Id: I4214db1f27120f9f9cd1413ccd7a5a7d095ff45d

show more ...

refactor(imx8mp): introduce BL2_SIZE and BL31_SIZE

No functional change.

Introduce BLx_SIZE defines and calculate the limits based on the
BLx_BASE and the BLx_SIZE define. Also make use of SZ_128K

refactor(imx8mp): introduce BL2_SIZE and BL31_SIZE

No functional change.

Introduce BLx_SIZE defines and calculate the limits based on the
BLx_BASE and the BLx_SIZE define. Also make use of SZ_128K to make it
easier to read. This is required for later BL31 PIE support since it
drops the calculation based on the BL31_LIMIT and BL31_BASE.

Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
Change-Id: Idae34c1dfcedd35238fe083149080a199d50eed0

show more ...

refactor(imx8mp): make use of setup_page_tables()

No functional change. Use the setup_page_tables() helper function which
does the three calls for us. Also the function has some logging support
whic

refactor(imx8mp): make use of setup_page_tables()

No functional change. Use the setup_page_tables() helper function which
does the three calls for us. Also the function has some logging support
which will be nice during debugging.

Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
Change-Id: I350965414939865220f745ef5b24d2cdc3095e7b

show more ...

refactor(imx8mp): cleanup the mmap region settings

Introduce the bl_regions array to gather all regions and make use of the
MAP_REGION_FLAT() macro. The array is than passed to mmap_add() to map
all

refactor(imx8mp): cleanup the mmap region settings

Introduce the bl_regions array to gather all regions and make use of the
MAP_REGION_FLAT() macro. The array is than passed to mmap_add() to map
all regions. While on it introduce some defines so the addr, size and
flags can be read more easily. No functional change done.

Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
Change-Id: I7f637beea61138a86d691cd78fba2dd17e4dc925

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feat(imx8m): make psci common code pie compatible

Swap the BL31_BASE define with the BL31_START symbol. This is required
for later added PIE support because the symbol location can be relocated
wher

feat(imx8m): make psci common code pie compatible

Swap the BL31_BASE define with the BL31_START symbol. This is required
for later added PIE support because the symbol location can be relocated
whereas the define can't be relocated. In case of disabled PIE support
BL31_START equals BL31_BASE and so we don't need a ifdef.

Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
Change-Id: Ic1bbf3af5b346898bfcbb207ffc27d9a5bdcaae7

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fix(imx8m): fix dram retention fsp_table access

The fsp_table access by [i-1] can cause invalid memory access in case of
i=0. This can be the case if no fsp_table is available. Fix this by
adding th

fix(imx8m): fix dram retention fsp_table access

The fsp_table access by [i-1] can cause invalid memory access in case of
i=0. This can be the case if no fsp_table is available. Fix this by
adding the idx variable which tracks the correct index.

Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
Change-Id: If2285517eb9fe837f3ad54360307a77a658bf62c

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fix(aarch64): make AArch64 FGT feature detection more robust

The ARMv8 ARM says about the values in the ID register scheme:

==== D17.1.3 Principles of the ID scheme for fields in ID registers ===
T

fix(aarch64): make AArch64 FGT feature detection more robust

The ARMv8 ARM says about the values in the ID register scheme:

==== D17.1.3 Principles of the ID scheme for fields in ID registers ===
The ID fields, which are either signed or unsigned, use increasing
numerical values to indicate increases in functionality. Therefore,
if a value of 0x1 indicates the presence of some instructions, then
the value 0x2 will indicate the presence of those instructions plus
some additional instructions or functionality. This means software
can be written in the form:
if (value >= number) {
// do something that relies on the value of the feature
}
=======================================================================

So to check for the presence of a certain architecture feature, we
should not check against a certain specific value, as it's done right
now in several cases.

Relax the test for Fine Grained Trapping (FGT) to just check against
the field being 0 or not.

This fixes TF-A crashing due to an unhandled exception, when running a
Linux kernel on an FVP enabling ARMv8.9 features. The value of
ID_AA64MMFR0_EL1.FGT went from 0b0001 to 0b0010 there.

Change-Id: Ic3f1625a7650306ed388a0660429ca8823c673c2
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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Merge "fix(cpus): fix cpu version check for Neoverse N2, V1" into integration

Merge "fix(cpus): workaround for Cortex-A510 erratum 2666669" into integration

Merge "feat(ethos-n)!: add support for SMMU streams" into integration

fix(cpus): fix cpu version check for Neoverse N2, V1

The CPU version check was moved wrongly down in N2 and missing in V1.
The patch fixes the issues.

Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>

fix(cpus): fix cpu version check for Neoverse N2, V1

The CPU version check was moved wrongly down in N2 and missing in V1.
The patch fixes the issues.

Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: Icb6e5285d6cc97fbe416fe1f0b1ab7afbd8a8809

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docs(imx8m): update for high assurance boot

Add a section into documentation listing the support for High Assurance
Boot (HABv4), note on the DRAM mapping, and reference to the external
documentatio

docs(imx8m): update for high assurance boot

Add a section into documentation listing the support for High Assurance
Boot (HABv4), note on the DRAM mapping, and reference to the external
documentation.

Signed-off-by: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com>
Change-Id: Iaca97f4ac2595e35de2664a880394519f96eca07

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feat(imx8m): add support for high assurance boot

Introduce support for High Assurance Boot (HABv4), which is used to
establish and extend the Root-of-Trust during FW loading at any given
boot stage.

feat(imx8m): add support for high assurance boot

Introduce support for High Assurance Boot (HABv4), which is used to
establish and extend the Root-of-Trust during FW loading at any given
boot stage.

This commit introduces support for HAB ROM Vector Table (RVT) API, which
is normally used by post-ROM code to authenticate additional boot images
(Kernel, FDT, FIT, etc.) that are taking part in the Root-of-Trust.

Signed-off-by: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com>
Change-Id: I780d308369824fa4850844eb9e91768e417166a0

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feat(imx8mp): add hab and map required memory blocks

In order for HAB to perform operations, memory regions has to be mapped
in TF-A, which HAB ROM code would use internally.

Include those memory b

feat(imx8mp): add hab and map required memory blocks

In order for HAB to perform operations, memory regions has to be mapped
in TF-A, which HAB ROM code would use internally.

Include those memory blocks for i.MX8M+ SoC. Of a special note, the DRAM
block is mapped with complete size available on the platform and uses
MT_RW attributes, this is required to minimize the size of translation
tables and provide a possibility to exchange the execution results
between EL3 and EL1&2, see details in [1].

Link: [1]: https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/16880
Signed-off-by: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com>
Change-Id: I986cdce434d1ec9ea8b3c0d5599edde55b9b30f8

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feat(imx8mn): add hab and map required memory blocks

In order for HAB to perform operations, memory regions has to be mapped
in TF-A, which HAB ROM code would use internally.

Include those memory b

feat(imx8mn): add hab and map required memory blocks

In order for HAB to perform operations, memory regions has to be mapped
in TF-A, which HAB ROM code would use internally.

Include those memory blocks for i.MX8MN SoC. Of a special note, the DRAM
block is mapped with complete size available on the platform and uses
MT_RW attributes, this is required to minimize the size of translation
tables and provide a possibility to exchange the execution results
between EL3 and EL1&2, see details in [1].

Link: [1]: https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/16880
Signed-off-by: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com>
Change-Id: If7a2b718658db452871e1ae56b71a4983e8ef2fe

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feat(imx8mm): add hab and map required memory blocks

In order for HAB to perform operations, memory regions has to be mapped
in TF-A, which HAB ROM code would use internally.

Include those memory b

feat(imx8mm): add hab and map required memory blocks

In order for HAB to perform operations, memory regions has to be mapped
in TF-A, which HAB ROM code would use internally.

Include those memory blocks for i.MX8MM SoC. Of a special note, the DRAM
block is mapped with complete size available on the platform and uses
MT_RW attributes, this is required to minimize the size of translation
tables and provide a possibility to exchange the execution results
between EL3 and EL1&2, see details in [1].

Link: [1]: https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/16880
Signed-off-by: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com>
Change-Id: I6a3a3d7105b85c2f4ab6ea6cfbca67c9a325eb11

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