| 00bb8c37 | 31-Jan-2022 |
Maninder Singh <maninder.singh_1@nxp.com> |
fix(nxp-ddr): apply Max CDD values for warm boot
Timing CFG 0 and Timing CFG 4 are ddr controller registers that
have been affected by 1d phy training during cold boot. They are
needed to be stored
fix(nxp-ddr): apply Max CDD values for warm boot
Timing CFG 0 and Timing CFG 4 are ddr controller registers that
have been affected by 1d phy training during cold boot. They are
needed to be stored and restored along with phy training values.
Signed-off-by: Maninder Singh <maninder.singh_1@nxp.com>
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I29c55256e74456515aaeb098e2e0e3475697a466
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| fa010569 | 21-Feb-2022 |
Maninder Singh <maninder.singh_1@nxp.com> |
fix(nxp-ddr): use CDDWW for write to read delay
we need to apply the value of CDD write to write for the write to
read CDD delay calculations. Since the current implementation always
provide a negat
fix(nxp-ddr): use CDDWW for write to read delay
we need to apply the value of CDD write to write for the write to
read CDD delay calculations. Since the current implementation always
provide a negative value of CDDwr so a value of zero was selected.
Signed-off-by: Maninder Singh <maninder.singh_1@nxp.com>
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I6829997d2ea6ba6cddaaab8332b82b8c66752d7e
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| c45791b2 | 02-Mar-2022 |
Jiafei Pan <Jiafei.Pan@nxp.com> |
fix(layerscape): fix errata a008850
Remove errata a008850 from ls1028a and ls1088a, it should
only be feasible for ls1020a, ls1043a and ls1046a.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Chang
fix(layerscape): fix errata a008850
Remove errata a008850 from ls1028a and ls1088a, it should
only be feasible for ls1020a, ls1043a and ls1046a.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I8ab84158a2ed6bb15b16d10f8796c3e86fc560a5
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| 9881bb93 | 21-Nov-2022 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "docs(spm): update threat model" into integration |
| 9aef90cc | 21-Nov-2022 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "docs(qemu): document steps to run in OpenCI" into integration |
| 31b5b36c | 14-Oct-2022 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
docs(spm): update threat model
Update SPM threat model for possible threats, from malicious
endpoints, related to interrupt management. The mitigations
are based on the guidance provided in FF-A v1.
docs(spm): update threat model
Update SPM threat model for possible threats, from malicious
endpoints, related to interrupt management. The mitigations
are based on the guidance provided in FF-A v1.1 EAC0 spec.
Change-Id: Ib9e26e3f1c60fe3a2734a67de1dcf1cea4883d38
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
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| a5667be0 | 15-Nov-2022 |
Harrison Mutai <harrison.mutai@arm.com> |
docs(qemu): document steps to run in OpenCI
Add details on how to run QEMU in OpenCI, and what tests are currently
supported.
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
Change-Id: I291e
docs(qemu): document steps to run in OpenCI
Add details on how to run QEMU in OpenCI, and what tests are currently
supported.
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
Change-Id: I291e4eb64a58c766519ff7dcac4841ae75c3934e
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| ca3f25dc | 21-Nov-2022 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Merge "fix(intel): fix UART baud rate and clock" into integration |
| 8e53b2fa | 01-Jul-2022 |
Sieu Mun Tang <sieu.mun.tang@intel.com> |
fix(intel): fix UART baud rate and clock
Revise the UART baud rate and clock for general platform build,
SIMIC build and EMU build.
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id:
fix(intel): fix UART baud rate and clock
Revise the UART baud rate and clock for general platform build,
SIMIC build and EMU build.
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: I62fefe7b96d5124e75d2810b4fbc1640422b1353
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| 8613c157 | 18-Nov-2022 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "docs(changelog): changelog for v2.8 release" into integration |
| f69b20dc | 18-Nov-2022 |
Joanna Farley <joanna.farley@arm.com> |
Merge "fix(docs): add v2.9 release schedule" into integration |
| a846d33a | 18-Nov-2022 |
Joanna Farley <joanna.farley@arm.com> |
fix(docs): add v2.9 release schedule
Signed-off-by: Joanna Farley <Joanna.Farley@arm.com>
Change-Id: I082461d7d21f63e3b8cbee37e8f01b8128e4b5a0 |
| 02fd5a17 | 17-Nov-2022 |
Olivier Deprez <olivier.deprez@arm.com> |
Merge changes I97687f18,I91d5718b into integration
* changes:
docs(spm): interrupt handling guidance FF-A v1.1 EAC0
docs(spm): partition runtime model and schedule modes |
| c7e698cf | 11-Nov-2022 |
Harrison Mutai <harrison.mutai@arm.com> |
fix(cpus): workaround for Cortex-X3 erratum 2615812
Cortex-X3 erratum 2615812 is a Cat B erratum that applies to revisions
r0p0, r1p0, and r1p1, and is still open. The workaround is to disable
the u
fix(cpus): workaround for Cortex-X3 erratum 2615812
Cortex-X3 erratum 2615812 is a Cat B erratum that applies to revisions
r0p0, r1p0, and r1p1, and is still open. The workaround is to disable
the use of the Full Retention power mode in the core (setting
WFI_RET_CTRL and WFE_RET_CTRL in CORTEX_X3_IMP_CPUPWRCTLR_EL1 to 0b000).
SDEN can be found here:
https://developer.arm.com/documentation/SDEN2055130/latest
Change-Id: I5ad66df3e18fc85a6b23f6662239494ee001d82f
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
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|
| 8fca0cdb | 17-Nov-2022 |
Olivier Deprez <olivier.deprez@arm.com> |
Merge changes from topic "ja/spm_doc" into integration
* changes:
docs(spm): ff-a v1.1 indirect message
docs(spm): s-el0 partition support update |
| db2bf3ac | 16-Nov-2022 |
Leo Yan <leo.yan@linaro.org> |
feat(qemu): increase size of bl2
Increases BL2 size to have room to enable security features (like
measurement and TPM).
Signed-off-by: Leo Yan <leo.yan@linaro.org>
Change-Id: Iba5e8923e2e154315499
feat(qemu): increase size of bl2
Increases BL2 size to have room to enable security features (like
measurement and TPM).
Signed-off-by: Leo Yan <leo.yan@linaro.org>
Change-Id: Iba5e8923e2e154315499e9bfce2e0aff0ccc8f95
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|
| 06afdd1e | 03-Oct-2022 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
docs(spm): interrupt handling guidance FF-A v1.1 EAC0
This patch documents the actions taken by Hafnium SPMC in response
to non-secure and secure interrupts.
Change-Id: I97687f188ca97aeb255e3e5b55d
docs(spm): interrupt handling guidance FF-A v1.1 EAC0
This patch documents the actions taken by Hafnium SPMC in response
to non-secure and secure interrupts.
Change-Id: I97687f188ca97aeb255e3e5b55d44ddf5d66b6e0
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
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|
| 0fa7fe59 | 15-Nov-2022 |
laurenw-arm <lauren.wehrmeister@arm.com> |
docs(changelog): changelog for v2.8 release
Change-Id: I1d99ea46ad527993ee786c34a67f94d74470f960
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com> |
| 03997f18 | 03-Oct-2022 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
docs(spm): partition runtime model and schedule modes
This patch documents the support for partition runtime models, call
chains and schedule modes in Hafnium SPMC.
Change-Id: I91d5718bb2c21d475499
docs(spm): partition runtime model and schedule modes
This patch documents the support for partition runtime models, call
chains and schedule modes in Hafnium SPMC.
Change-Id: I91d5718bb2c21d475499e402f6f27076930336cb
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
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|
| b688120c | 16-Nov-2022 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "docs(marvell): fix typo 8K => A8K" into integration |
| 53e3b385 | 26-Oct-2022 |
J-Alves <joao.alves@arm.com> |
docs(spm): ff-a v1.1 indirect message
Update secure partition manager documentation to include
FF-A v1.1 indirect messaging implementation.
Signed-off-by: J-Alves <joao.alves@arm.com>
Change-Id: If
docs(spm): ff-a v1.1 indirect message
Update secure partition manager documentation to include
FF-A v1.1 indirect messaging implementation.
Signed-off-by: J-Alves <joao.alves@arm.com>
Change-Id: Ifbca45347f775080ef98ac896d31650204318ba4
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| 71061819 | 16-Nov-2022 |
Manish V Badarkhe <manish.badarkhe@arm.com> |
Merge changes If90a18ee,I02e88f8c,Iea447fb5,Ie0570481,Ieeb14cfc into integration
* changes:
docs: add top level section numbering
docs(build): clarify getting started section
docs(build): clar
Merge changes If90a18ee,I02e88f8c,Iea447fb5,Ie0570481,Ieeb14cfc into integration
* changes:
docs: add top level section numbering
docs(build): clarify getting started section
docs(build): clarify docs building instructions
fix(docs): prevent a sphinx warning
fix(docs): prevent a virtual environment from failing a build
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|
| 54c52bcb | 16-Nov-2022 |
Olivier Deprez <olivier.deprez@arm.com> |
Merge "docs(spm): update FF-A manifest binding" into integration |
| c65bf2d1 | 27-Oct-2022 |
Boyan Karatotev <boyan.karatotev@arm.com> |
docs: add top level section numbering
Top level sections are not numbered. Adding numbers makes referring to
sections easier. For example the Maintainers page changes from
"about/3.1" to simply "1.3
docs: add top level section numbering
Top level sections are not numbered. Adding numbers makes referring to
sections easier. For example the Maintainers page changes from
"about/3.1" to simply "1.3.1".
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: If90a18ee8d6a6858d58f0687f31ea62b69399e04
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| b50838ba | 27-Oct-2022 |
Boyan Karatotev <boyan.karatotev@arm.com> |
docs(build): clarify getting started section
The Getting started section is very difficult to follow. Building the
fip comes before building the files it needs, the BL33 requirement is
given in a so
docs(build): clarify getting started section
The Getting started section is very difficult to follow. Building the
fip comes before building the files it needs, the BL33 requirement is
given in a somewhat hand wavy way, and the Arm Developer website
download provides a lot of targets and the guide is not clear which ones
are needed on download.
Swapping the initial build and supporting tools sections makes the flow
more natural and the supporting tools section then becomes clear.
Explicitly mentioning the GCC targets avoids confusion for people less
familiar with the project (eg. new starters).
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: I02e88f8c279db6d8eda68f634e8473c02b733963
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|