feat(optee): add loading OP-TEE image via an SMC

This adds the ability to load the OP-TEE image via an SMC called from
non-secure userspace rather than loading it during boot. This should
only be ut

feat(optee): add loading OP-TEE image via an SMC

This adds the ability to load the OP-TEE image via an SMC called from
non-secure userspace rather than loading it during boot. This should
only be utilized on platforms that can ensure security is maintained up
until the point the SMC is invoked as it breaks the normal barrier
between the secure and non-secure world.

Signed-off-by: Jeffrey Kardatzke <jkardatzke@google.com>
Change-Id: I21cfa9699617c493fa4190f01d1cbb714e7449cc

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docs(rme): update RMM-EL3 Boot Manifest structure description

This patch updates description of RMM-EL3 Boot Manifest
structure and its corresponding diagram and tables with DRAM
layout data.

Signe

docs(rme): update RMM-EL3 Boot Manifest structure description

This patch updates description of RMM-EL3 Boot Manifest
structure and its corresponding diagram and tables with DRAM
layout data.

Signed-off-by: AlexeiFedorov <Alexei.Fedorov@arm.com>
Change-Id: I1b092bc1ad5f1c7909d25c1a0dc89c2b210ada27

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feat(rme): read DRAM information from FVP DTB

This patch builds on the previous patch by implementing
support for reading NS DRAM layout of FVP model from
HW_CONFIG Device tree.

Macro _RMMD_MANIFES

feat(rme): read DRAM information from FVP DTB

This patch builds on the previous patch by implementing
support for reading NS DRAM layout of FVP model from
HW_CONFIG Device tree.

Macro _RMMD_MANIFEST_VERSION is renamed to
SET_RMMD_MANIFEST_VERSION to suppress MISRA-C
"rule MC3R1.D4.5: (advisory) Identifiers in
the same name space with overlapping visibility
should be typographically unambiguous" warning

Signed-off-by: AlexeiFedorov <Alexei.Fedorov@arm.com>
Change-Id: Ifc2461b4441a1efdd4b7c656ab4d15e62479f77b

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Merge "feat(morello): add support for HW_CONFIG" into integration

Merge "perf(imx): speed-up console/uart TX using FIFO" into integration

Merge "docs(measured-boot): fix few typos" into integration

docs(measured-boot): fix few typos

Fixed few typos in the measured boot POC document.

Change-Id: I122c069bbde51febed12c54e2c4a4985b009ef5f
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

perf(imx): speed-up console/uart TX using FIFO

The current putc version test for TXEMPTY bit set (#6) instead
of waiting for TXFULL bit clear (#4), that slows the global
boot time as we are not taki

perf(imx): speed-up console/uart TX using FIFO

The current putc version test for TXEMPTY bit set (#6) instead
of waiting for TXFULL bit clear (#4), that slows the global
boot time as we are not taking benefit of the 32-byte FIFO.

We then need to implement the flush function to be sure the
transmit is complete (FIFO and shift register empty).

Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
Change-Id: I54873a5203e2afdc230e44ce73284e7a80985b4f

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feat(morello): add support for HW_CONFIG

This patch add support to load HW_CONFIG in BL2 and pass it to
bootloader stages BL31 and BL33.

Signed-off-by: Patrik Berglund <patrik.berglund@arm.com>
Cha

feat(morello): add support for HW_CONFIG

This patch add support to load HW_CONFIG in BL2 and pass it to
bootloader stages BL31 and BL33.

Signed-off-by: Patrik Berglund <patrik.berglund@arm.com>
Change-Id: I646fabed83dbca5322a59a399de5194cfef474ad

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Merge "fix(cpus): workaround for Cortex-A78C erratum 2772121" into integration

Merge "feat(plat/tc): enable MPAM functionality of L3 DSU cache" into integration

feat(plat/tc): enable MPAM functionality of L3 DSU cache

The L3 cache in the DSU supports the Memory System Resources
Partitioning and Monitoring (MPAM). The MPAM specific registers in the
DSU are a

feat(plat/tc): enable MPAM functionality of L3 DSU cache

The L3 cache in the DSU supports the Memory System Resources
Partitioning and Monitoring (MPAM). The MPAM specific registers in the
DSU are accessed through utility bus of DSU that are memory mapped from
0x1_0000_1000.

Signed-off-by: Davidson K <davidson.kumaresan@arm.com>
Change-Id: I2798181d599228e96dd4c0043a2ccd94668c7e20

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Merge "fix(cpus): workaround for Cortex-A510 erratum 2684597" into integration

Merge "fix(psci): tighten psci_power_down_wfi behaviour" into integration

docs(spm): add other-s-interrupts-action field to sp manifest

Also, the `run-time-model` field is removed from SP manifest binding
as it is not supported by Hafnium(SPMC).

Change-Id: Id8a91b2608791

docs(spm): add other-s-interrupts-action field to sp manifest

Also, the `run-time-model` field is removed from SP manifest binding
as it is not supported by Hafnium(SPMC).

Change-Id: Id8a91b2608791667e6285b3c5b879ec84612149d
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

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Merge "docs(rme): improve OOB instruction for RME" into integration

docs(rme): improve OOB instruction for RME

This patch reworks the existing OOB instructions for RME enabled
TF-A.

Signed-off-by: Soby Mathew <soby.mathew@arm.com>
Change-Id: Icaeaf48c7061feaad4b1bb

docs(rme): improve OOB instruction for RME

This patch reworks the existing OOB instructions for RME enabled
TF-A.

Signed-off-by: Soby Mathew <soby.mathew@arm.com>
Change-Id: Icaeaf48c7061feaad4b1bb92388954694705e45c

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fix(cpus): workaround for Cortex-A510 erratum 2684597

Cortex-A510 erratum 2684597 is a Cat B erratum that applies to revisions
r0p0, r0p1, r0p2, r0p3, r1p0, r1p1 and r1p2. It is fixed in r1p3. The
w

fix(cpus): workaround for Cortex-A510 erratum 2684597

Cortex-A510 erratum 2684597 is a Cat B erratum that applies to revisions
r0p0, r0p1, r0p2, r0p3, r1p0, r1p1 and r1p2. It is fixed in r1p3. The
workaround is to execute a TSB CSYNC and DSB before executing WFI for
power down.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN1873361/latest
https://developer.arm.com/documentation/SDEN1873351/latest

Change-Id: Ic0b24b600bc013eb59c797401fbdc9bda8058d6d
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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Merge changes from topic "fix_misra_partition_mmc" into integration

* changes:
fix(mmc): align part config type
fix(mmc): do not modify r_data in mmc_send_cmd()
fix(mmc): explicitly check oper

Merge changes from topic "fix_misra_partition_mmc" into integration

* changes:
fix(mmc): align part config type
fix(mmc): do not modify r_data in mmc_send_cmd()
fix(mmc): explicitly check operators precedence
fix(partition): add U suffix for unsigned numbers
fix(partition): add missing curly braces

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Merge "docs: change security advisories notification channel" into integration

fix(psci): tighten psci_power_down_wfi behaviour

A processing element should never return from a wfi, however, due to a
hardware bug, certain CPUs may wake up because of an external event.
This patc

fix(psci): tighten psci_power_down_wfi behaviour

A processing element should never return from a wfi, however, due to a
hardware bug, certain CPUs may wake up because of an external event.
This patch tightens the behaviour of the common power down sequence, it
ensures the routine never returns by entering a wfi loop at its end. It
aligns with the behaviour of the platform implementations.

Change-Id: I36d8b0c64eccb71035bf164b4cd658d66ed7beb4
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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Merge "feat(fiptool): handle FIP in a disk partition" into integration

Merge "feat(rss): add TC platform UUIDs for RSS images" into integration

fix(mpam): run-time checks for mpam save/restore routines

With "ENABLE_MPAM_FOR_LOWER_ELS" and "CTX_INCLUDE_EL2_REGS" build
options enabled, MPAM EL2 registers would be saved/restored as part of
con

fix(mpam): run-time checks for mpam save/restore routines

With "ENABLE_MPAM_FOR_LOWER_ELS" and "CTX_INCLUDE_EL2_REGS" build
options enabled, MPAM EL2 registers would be saved/restored as part of
context management. Context save/restore routines as of now would
proceed to access all of MPAM EL2 registers without any runtime checks.
MPAM specification states that MPAMHCR_EL2 should only be accessed if
MPAMIDR_EL1.HAS_HCR is "1". Likewise, MPAMIDR_EL1.VPMR_MAX has to be
probed to obtain the maximum supported MPAMVPM<x>_EL2 before accessing
corresponding MPAMVPM<x>_EL2 registers. Since runtime checks are not
being made, an exception would be raised if the platform under test
doesn't support one of the registers. On Neoverse reference design
platforms, an exception is being raised while MPAMVPM2_EL2 or above are
accessed. Neoverse reference design platforms support only registers
till MPAMVPM1_EL2 at this point.

To resolve this, add sufficient runtime checks in MPAM EL2 context
save/restore routines. As part of the new save/restore routines,
MPAMIDR_EL1.HAS_HCR and MPAMIDR_EL1.VPMR_MAX are probed for the right
set of registers to be saved and restored.

CC: Davidson Kumaresan <davidson.kumaresan@arm.com>
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: I2e3affd23091023b287b2bd5057a4a549037b611

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feat(fiptool): handle FIP in a disk partition

When FIP is programmed in a disk partition, fiptool cannot be used
directly; this forces the user to temporarily copy the partition
to a file, apply fip

feat(fiptool): handle FIP in a disk partition

When FIP is programmed in a disk partition, fiptool cannot be used
directly; this forces the user to temporarily copy the partition
to a file, apply fiptool and copy back the file. This is caused by
fstat() that returns zero file size on a block special file, thus
making fiptool commands info, update, unpack and remove to exit.

For either Linux host or Linux target, recover the partition size
with ioctl() and use it as FIP file size. E.g.:
fiptool info /dev/disk/by-partlabel/fip-a
fiptool info /dev/mtdblock4

While there, rework two identical error log messages to provide
more details about the failure and update the date in copyright.

Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com>
Change-Id: I7cab60e577422d94c24ba7e39458f58bcebc2336

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