fix(cpus): workaround for Neoverse N2 erratum 2743089

Neoverse N2 erratum 2743089 is a Cat B erratum that applies to
all revisions <=r0p2 and is fixed in r0p3. The workaround is to
insert a dsb befo

fix(cpus): workaround for Neoverse N2 erratum 2743089

Neoverse N2 erratum 2743089 is a Cat B erratum that applies to
all revisions <=r0p2 and is fixed in r0p3. The workaround is to
insert a dsb before the isb in the power down sequence.

SDEN documentation:
https://developer.arm.com/documentation/SDEN1982442/latest

Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: Idec862226bd32c91374a8bbd5d73d7ee480a34d9

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Merge changes I0362da46,I8ee7c16c into integration

* changes:
fix(cpus): workaround for Cortex-A78 erratum 2772019
fix(cpus): workaround for Neoverse V1 erratum 2743093

feat(fvp): emulate trapped RNDR

When a platform decides to use FEAT_RNG_TRAP, every RNDR or RNDRSS read
will trap into EL3. The platform can then emulate those instructions, by
either executing the

feat(fvp): emulate trapped RNDR

When a platform decides to use FEAT_RNG_TRAP, every RNDR or RNDRSS read
will trap into EL3. The platform can then emulate those instructions, by
either executing the real CPU instructions, potentially conditioning the
results, or use rate-limiting or filtering to protect the hardware
entropy pool. Another possiblitiy would be to use some platform specific
TRNG device to get entropy and returning this.

To demonstrate platform specific usage, add a demo implementation for the
FVP: It will execute the actual CPU instruction and just return the
result. This should serve as reference code to implement platform specific
policies.

We change the definition of read_rndr() and read_rndrrs() to use the
alternative sysreg encoding, so that all assemblers can handle that.

Add documentation about the new platform specific RNG handler function.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Change-Id: Ibce817b3b06ad20129d15531b81402e3cc3e9a9e

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feat(el3-runtime): introduce system register trap handler

At the moment we only handle SMC traps from lower ELs, but ignore any
other synchronous traps and just panic.
To cope with system register t

feat(el3-runtime): introduce system register trap handler

At the moment we only handle SMC traps from lower ELs, but ignore any
other synchronous traps and just panic.
To cope with system register traps, which we might need to emulate,
introduce a C function to handle those traps, and wire that up in the
exception handler to be called.

We provide a dispatcher function (in C), that will call platform
specific implementation for certain (classes of) system registers.
For now this is empty.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Change-Id: If147bcb49472eb02791498700300926afbcf75ff

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fix(cpus): workaround for Cortex-A78 erratum 2772019

Cortex-A78 erratum 2772019 is a Cat B erratum that applies to
all revisions <=r1p2 and is still open. The workaround is to
insert a dsb before th

fix(cpus): workaround for Cortex-A78 erratum 2772019

Cortex-A78 erratum 2772019 is a Cat B erratum that applies to
all revisions <=r1p2 and is still open. The workaround is to
insert a dsb before the isb in the power down sequence.

SDEN documentation:
https://developer.arm.com/documentation/SDEN1401784/latest

Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: I0362da463eca777aa7a385bcdeb39b8549799f02

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fix(cpus): workaround for Neoverse V1 erratum 2743093

Neoverse V1 erratum 2743093 is a Cat B erratum that applies to
all revisions <=r1p2 and is still open. The workaround is to
insert a dsb before

fix(cpus): workaround for Neoverse V1 erratum 2743093

Neoverse V1 erratum 2743093 is a Cat B erratum that applies to
all revisions <=r1p2 and is still open. The workaround is to
insert a dsb before the isb in the power down sequence.

SDEN documentation:
https://developer.arm.com/documentation/SDEN1401781/latest

Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: I8ee7c16c14c4fd6ee35d20c855273ecfce0d1b32

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Merge "fix(el3-spmc): report execution state in partition info get" into integration

Merge "feat(tc): add delegated attest and measurement tests" into integration

fix(tc): change the properties of optee reserved memory

make it part of the restricted dma pool to ensure it is not used for
general dma operations.

Change-Id: Ia14738de70b4d7719d7460ed8d16e727aea8

fix(tc): change the properties of optee reserved memory

make it part of the restricted dma pool to ensure it is not used for
general dma operations.

Change-Id: Ia14738de70b4d7719d7460ed8d16e727aea8d8c4
Signed-off-by: Davidson K <davidson.kumaresan@arm.com>

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feat(tc): use smmu 700

Enable smmu for gpu and dpu

Signed-off-by: Davidson K <davidson.kumaresan@arm.com>
Change-Id: I6f4cffdc835dc542904b0a15b1db9a3382b78c08

Merge "fix(gic): wrap cache enabled assert under plat_can_cmo" into integration

refactor(st): remove unused io_mmc driver

This driver was used when STM32MP_USE_STM32IMAGE was enabled. This flag
is now removed, so the ST io_mmc driver can now be removed.

Signed-off-by: Yann Gau

refactor(st): remove unused io_mmc driver

This driver was used when STM32MP_USE_STM32IMAGE was enabled. This flag
is now removed, so the ST io_mmc driver can now be removed.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I3c1280dec8926b921534c81e143e86cfe6d4ee0d

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docs: deprecate io_dummy driver

This drivers was only used by one upstream platform: STM32MP1 but only
when enabling the flag STM32MP_USE_STM32IMAGE. This flag and the
corresponding code is now remo

docs: deprecate io_dummy driver

This drivers was only used by one upstream platform: STM32MP1 but only
when enabling the flag STM32MP_USE_STM32IMAGE. This flag and the
corresponding code is now removed from TF-A. The driver can then be
set to deprecated. It will be removed after v2.9 tag.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: Ib8242a7291c7011d7f96a6a83609ec1996dce520

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Merge "fix(intel): add mailbox error return status for FCS_DECRYPTION" into integration

Merge "fix(arm): arm_rotpk_header undefined reference" into integration

fix(arm): arm_rotpk_header undefined reference

Moving ARM_ROTPK_S to default to arm_dev_rotpk.S as it was not being
set for Juno cryptocell and this should be the value in most cases.

Change-Id: I5

fix(arm): arm_rotpk_header undefined reference

Moving ARM_ROTPK_S to default to arm_dev_rotpk.S as it was not being
set for Juno cryptocell and this should be the value in most cases.

Change-Id: I56a5a4e61f1ca728b87322b0b09a0d73ed1d5ee0
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>

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feat(tc): add delegated attest and measurement tests

This patch adds Delegated Attestation and Measured Boot tests to the
plat/arm/board/tc platform.
The test suite can be activated by adding the bu

feat(tc): add delegated attest and measurement tests

This patch adds Delegated Attestation and Measured Boot tests to the
plat/arm/board/tc platform.
The test suite can be activated by adding the build time option
`PLATFORM_TEST=1` to the make command. In this case the boot sequence is
not finished, plat_error_handler is called after the tests are run
(regardless of the test result.)

The actual test code is coming from the Trusted-Firmware-M project. Some
of the files of the tf-m-tests and tf-m-extras repo are linked to the
BL31 image.

Versions used for testing:
https://git.trustedfirmware.org/TF-M/tf-m-tests
614e8c358377e4146e8ee13d1246e59d01b4bf1b

https: //git.trustedfirmware.org/TF-M/tf-m-extras
3be9fdd557e6df449de93c2101973fb011699b3d

Change-Id: I98f0f5f760a39d2d7e0dd11d33663ddb75f0b6fc
Signed-off-by: Mate Toth-Pal <mate.toth-pal@arm.com>

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Merge "fix(xilinx): resolve integer handling issue" into integration

Merge "fix(intel): missing NCORE CCU snoop filter fix in BL2" into integration

fix(xilinx): resolve integer handling issue

OEN Number 48 to 63 is for Trusted App and OS.
GET_SMC_OEN limits the return value of OEN number to 63 by bitwise AND
operation with 0x3F. Thus the upper

fix(xilinx): resolve integer handling issue

OEN Number 48 to 63 is for Trusted App and OS.
GET_SMC_OEN limits the return value of OEN number to 63 by bitwise AND
operation with 0x3F. Thus the upper limit check for OEN value returned
by GET_SMC_OEN is not required.
Removing the upper limit check for the OEN value returned by GET_SMC_OEN
resolves integer handling issue CONSTANT_EXPRESSION_RESULT

Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>
Change-Id: Ie04a4e2fb7cc85ec6055a5662736a805a89f7085

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Merge changes Ibb593369,I9cc984dd into integration

* changes:
fix(el3_runtime): allow SErrors when executing in EL3
fix(el3_runtime): do not save scr_el3 during EL3 entry

Merge changes I2b23e7c8,I779587af,Ic46de7a4,If753e987,I00171b05, ... into integration

* changes:
fix(layerscape): unlock write access SMMU_CBn_ACTLR
fix(nxp-ddr): add checking return value
fea

Merge changes I2b23e7c8,I779587af,Ic46de7a4,If753e987,I00171b05, ... into integration

* changes:
fix(layerscape): unlock write access SMMU_CBn_ACTLR
fix(nxp-ddr): add checking return value
feat(lx2): enable OCRAM ECC
fix(nxp-tools): fix coverity issue
fix(nxp-ddr): fix coverity issue
fix(nxp-ddr): fix underrun coverity issue
fix(nxp-drivers): fix sd secure boot failure
feat(lx2): support more variants
fix(lx2): init global data before using it
fix(ls1046a): 4 keys secureboot failure resolved
fix(nxp-crypto): fix secure boot assert inclusion
fix(nxp-crypto): fix coverity issue
fix(nxp-drivers): fix fspi coverity issue
fix(nxp-drivers): fix tzc380 memory regions config
fix(layerscape): fix nv_storage assert checking
fix(nxp-ddr): apply Max CDD values for warm boot
fix(nxp-ddr): use CDDWW for write to read delay
fix(layerscape): fix errata a008850

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Merge "fix(gpt_rme): fix compilation error for gpt_rme.c" into integration

Merge changes from topic "qemu_sel2" into integration

* changes:
docs(build): describes the SPMC_OPTEE build option
feat(qemu): support el3 spmc
feat(el3-spmc): make platform logical partition

Merge changes from topic "qemu_sel2" into integration

* changes:
docs(build): describes the SPMC_OPTEE build option
feat(qemu): support el3 spmc
feat(el3-spmc): make platform logical partition optional
feat(qemu): support s-el2 spmc
feat(qemu): update abi between spmd and spmc
fix(sptool): add dependency to SP image

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fix(intel): add mailbox error return status for FCS_DECRYPTION

Add 2 more mailbox error return status for FCS_DECRYPTION when sending
mailbox command to SDM

Signed-off-by: Sieu Mun Tang <sieu.mun.t

fix(intel): add mailbox error return status for FCS_DECRYPTION

Add 2 more mailbox error return status for FCS_DECRYPTION when sending
mailbox command to SDM

Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: Ifff4faa397232cc0080f9fca6f6948ac305915c4

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