Merge changes I1b092bc1,Ifc2461b4,I5176caa5 into integration

* changes:
docs(rme): update RMM-EL3 Boot Manifest structure description
feat(rme): read DRAM information from FVP DTB
feat(rme): s

Merge changes I1b092bc1,Ifc2461b4,I5176caa5 into integration

* changes:
docs(rme): update RMM-EL3 Boot Manifest structure description
feat(rme): read DRAM information from FVP DTB
feat(rme): set DRAM information in Boot Manifest platform data

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fix(versal-net): populate gic v3 rdist data statically

Currently gicv3_rdistif_probe() is called per CPU. In case of maxcpus=1,
only 1 core is initialized and gicr_base_addrs initialized for CPU 0
o

fix(versal-net): populate gic v3 rdist data statically

Currently gicv3_rdistif_probe() is called per CPU. In case of maxcpus=1,
only 1 core is initialized and gicr_base_addrs initialized for CPU 0
only. Because of this assertion is raised during Linux system suspend.

During Linux suspend, platform callback saves GIC v3 state which
internally invokes arm_gicv3_distif_pre_save(). This function tries to use
gicr_base for all CPUs. Since GICR base address for secondary CPUs are not
initialized, it raises assertion.

To fix the issue, populate GIC v3 rdist data statically (similar to Versal)
instead of dynamically initializing GIC v3 rdist per CPU.

Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Change-Id: I98c97c03e451d05f4ebac358e197617ab9d9b71f

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feat(versal-net): add jtag dcc support

Add support for JTAG Debug Communication Channel(DCC), using the dcc
console driver, for Versal NET platform.
UART0/UART1 is not configured when the JTAG DCC i

feat(versal-net): add jtag dcc support

Add support for JTAG Debug Communication Channel(DCC), using the dcc
console driver, for Versal NET platform.
UART0/UART1 is not configured when the JTAG DCC is used as console for
the platform.
Though DCC is not using any UART, VERSAL_NET_UART_BASE needs
to be defined in the platform code. If its not defined, build errors
are observed.
Now VERSAL_NET_UART_BASE by default points to UART0 base.
Check for valid console(pl011, pl011_0, pl011_1, dcc) is
being done in the platform makefile, the error condition in
setting the value of VERSAL_NET_UART_BASE is redundant, thus the error
message is removed from the code.

Change-Id: I1085433055abea13526230cff4d4183ff7a01477
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>

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feat(optee): add loading OP-TEE image via an SMC

This adds the ability to load the OP-TEE image via an SMC called from
non-secure userspace rather than loading it during boot. This should
only be ut

feat(optee): add loading OP-TEE image via an SMC

This adds the ability to load the OP-TEE image via an SMC called from
non-secure userspace rather than loading it during boot. This should
only be utilized on platforms that can ensure security is maintained up
until the point the SMC is invoked as it breaks the normal barrier
between the secure and non-secure world.

Signed-off-by: Jeffrey Kardatzke <jkardatzke@google.com>
Change-Id: I21cfa9699617c493fa4190f01d1cbb714e7449cc

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docs(rme): update RMM-EL3 Boot Manifest structure description

This patch updates description of RMM-EL3 Boot Manifest
structure and its corresponding diagram and tables with DRAM
layout data.

Signe

docs(rme): update RMM-EL3 Boot Manifest structure description

This patch updates description of RMM-EL3 Boot Manifest
structure and its corresponding diagram and tables with DRAM
layout data.

Signed-off-by: AlexeiFedorov <Alexei.Fedorov@arm.com>
Change-Id: I1b092bc1ad5f1c7909d25c1a0dc89c2b210ada27

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feat(rme): read DRAM information from FVP DTB

This patch builds on the previous patch by implementing
support for reading NS DRAM layout of FVP model from
HW_CONFIG Device tree.

Macro _RMMD_MANIFES

feat(rme): read DRAM information from FVP DTB

This patch builds on the previous patch by implementing
support for reading NS DRAM layout of FVP model from
HW_CONFIG Device tree.

Macro _RMMD_MANIFEST_VERSION is renamed to
SET_RMMD_MANIFEST_VERSION to suppress MISRA-C
"rule MC3R1.D4.5: (advisory) Identifiers in
the same name space with overlapping visibility
should be typographically unambiguous" warning

Signed-off-by: AlexeiFedorov <Alexei.Fedorov@arm.com>
Change-Id: Ifc2461b4441a1efdd4b7c656ab4d15e62479f77b

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Merge "feat(morello): add support for HW_CONFIG" into integration

Merge "perf(imx): speed-up console/uart TX using FIFO" into integration

Merge "docs(measured-boot): fix few typos" into integration

docs(measured-boot): fix few typos

Fixed few typos in the measured boot POC document.

Change-Id: I122c069bbde51febed12c54e2c4a4985b009ef5f
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

perf(imx): speed-up console/uart TX using FIFO

The current putc version test for TXEMPTY bit set (#6) instead
of waiting for TXFULL bit clear (#4), that slows the global
boot time as we are not taki

perf(imx): speed-up console/uart TX using FIFO

The current putc version test for TXEMPTY bit set (#6) instead
of waiting for TXFULL bit clear (#4), that slows the global
boot time as we are not taking benefit of the 32-byte FIFO.

We then need to implement the flush function to be sure the
transmit is complete (FIFO and shift register empty).

Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
Change-Id: I54873a5203e2afdc230e44ce73284e7a80985b4f

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feat(morello): add support for HW_CONFIG

This patch add support to load HW_CONFIG in BL2 and pass it to
bootloader stages BL31 and BL33.

Signed-off-by: Patrik Berglund <patrik.berglund@arm.com>
Cha

feat(morello): add support for HW_CONFIG

This patch add support to load HW_CONFIG in BL2 and pass it to
bootloader stages BL31 and BL33.

Signed-off-by: Patrik Berglund <patrik.berglund@arm.com>
Change-Id: I646fabed83dbca5322a59a399de5194cfef474ad

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Merge "fix(cpus): workaround for Cortex-A78C erratum 2772121" into integration

Merge "feat(plat/tc): enable MPAM functionality of L3 DSU cache" into integration

feat(plat/tc): enable MPAM functionality of L3 DSU cache

The L3 cache in the DSU supports the Memory System Resources
Partitioning and Monitoring (MPAM). The MPAM specific registers in the
DSU are a

feat(plat/tc): enable MPAM functionality of L3 DSU cache

The L3 cache in the DSU supports the Memory System Resources
Partitioning and Monitoring (MPAM). The MPAM specific registers in the
DSU are accessed through utility bus of DSU that are memory mapped from
0x1_0000_1000.

Signed-off-by: Davidson K <davidson.kumaresan@arm.com>
Change-Id: I2798181d599228e96dd4c0043a2ccd94668c7e20

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Merge "fix(cpus): workaround for Cortex-A510 erratum 2684597" into integration

Merge "fix(psci): tighten psci_power_down_wfi behaviour" into integration

docs(spm): add other-s-interrupts-action field to sp manifest

Also, the `run-time-model` field is removed from SP manifest binding
as it is not supported by Hafnium(SPMC).

Change-Id: Id8a91b2608791

docs(spm): add other-s-interrupts-action field to sp manifest

Also, the `run-time-model` field is removed from SP manifest binding
as it is not supported by Hafnium(SPMC).

Change-Id: Id8a91b2608791667e6285b3c5b879ec84612149d
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

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Merge "docs(rme): improve OOB instruction for RME" into integration

docs(rme): improve OOB instruction for RME

This patch reworks the existing OOB instructions for RME enabled
TF-A.

Signed-off-by: Soby Mathew <soby.mathew@arm.com>
Change-Id: Icaeaf48c7061feaad4b1bb

docs(rme): improve OOB instruction for RME

This patch reworks the existing OOB instructions for RME enabled
TF-A.

Signed-off-by: Soby Mathew <soby.mathew@arm.com>
Change-Id: Icaeaf48c7061feaad4b1bb92388954694705e45c

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fix(cpus): workaround for Cortex-A510 erratum 2684597

Cortex-A510 erratum 2684597 is a Cat B erratum that applies to revisions
r0p0, r0p1, r0p2, r0p3, r1p0, r1p1 and r1p2. It is fixed in r1p3. The
w

fix(cpus): workaround for Cortex-A510 erratum 2684597

Cortex-A510 erratum 2684597 is a Cat B erratum that applies to revisions
r0p0, r0p1, r0p2, r0p3, r1p0, r1p1 and r1p2. It is fixed in r1p3. The
workaround is to execute a TSB CSYNC and DSB before executing WFI for
power down.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN1873361/latest
https://developer.arm.com/documentation/SDEN1873351/latest

Change-Id: Ic0b24b600bc013eb59c797401fbdc9bda8058d6d
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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Merge changes from topic "fix_misra_partition_mmc" into integration

* changes:
fix(mmc): align part config type
fix(mmc): do not modify r_data in mmc_send_cmd()
fix(mmc): explicitly check oper

Merge changes from topic "fix_misra_partition_mmc" into integration

* changes:
fix(mmc): align part config type
fix(mmc): do not modify r_data in mmc_send_cmd()
fix(mmc): explicitly check operators precedence
fix(partition): add U suffix for unsigned numbers
fix(partition): add missing curly braces

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Merge "docs: change security advisories notification channel" into integration

fix(psci): tighten psci_power_down_wfi behaviour

A processing element should never return from a wfi, however, due to a
hardware bug, certain CPUs may wake up because of an external event.
This patc

fix(psci): tighten psci_power_down_wfi behaviour

A processing element should never return from a wfi, however, due to a
hardware bug, certain CPUs may wake up because of an external event.
This patch tightens the behaviour of the common power down sequence, it
ensures the routine never returns by entering a wfi loop at its end. It
aligns with the behaviour of the platform implementations.

Change-Id: I36d8b0c64eccb71035bf164b4cd658d66ed7beb4
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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Merge "feat(fiptool): handle FIP in a disk partition" into integration