fix(stm32mp1): properly check PSCI functions return

The psci_get_pstate_* helpers return unsigned int values,
update the code accordingly. Remove the useless pstate variable.
This corrects MISRA C20

fix(stm32mp1): properly check PSCI functions return

The psci_get_pstate_* helpers return unsigned int values,
update the code accordingly. Remove the useless pstate variable.
This corrects MISRA C2012-14.4:
The controlling expression of an if statement and the controlling
expression of an iteration-statement shall have essentially Boolean
type.

Change-Id: Idc7e756f4ba2bc0d66a327763013f77f86fe16b2
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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Merge "docs: fix syntax error in note" into integration

chore: rename Makalu to Cortex-A715

Change-Id: I017c955cb643e2befb6b01e1b5a07c22172b08b9
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

feat(cpus): wrappers to propagate AArch32 errata info

AArch32 is not being ported to the errata framework. However, the
runtime errata list is needed at runtime for the upcoming errata ABI.
Add wrap

feat(cpus): wrappers to propagate AArch32 errata info

AArch32 is not being ported to the errata framework. However, the
runtime errata list is needed at runtime for the upcoming errata ABI.
Add wrappers to populate this information and make it accessible in the
same way as AArch64.

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: I084720f34d6ed4e00e94b09babd3c90a5393298a

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feat(cpus): add a way to automatically report errata

Using the errata framework per-cpu data structure, errata can all be
reported automatically through a single standard errata reporter which
can r

feat(cpus): add a way to automatically report errata

Using the errata framework per-cpu data structure, errata can all be
reported automatically through a single standard errata reporter which
can replace the cpu-specific ones.

This reporter can also enforce the ordering requirement of errata.

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: I7d2d5ac5bcb9d21aed0d560d7d23919a323ffdab

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feat(cpus): add a concise way to implement AArch64 errata

Errata implementation involves adding a lot of boilerplate to random
places with just conventions on how to do them. Copy pasting is the
usu

feat(cpus): add a concise way to implement AArch64 errata

Errata implementation involves adding a lot of boilerplate to random
places with just conventions on how to do them. Copy pasting is the
usual method for doing this. The result is an error-prone and verbose
patch that is a nightmare to get through review.

Errata workarounds have a very large degree of similarity - most of them
involve setting a bit at reset. As such most of the boilerplate is not
strictly necessary. To solve this, add a collection of assembly macros
to wrap errata implementations such that only the actual mitigations
need to be written. A new erratum mitigation looks something like:

workaround_reset_start cortex_a77, ERRATUM(1925769), ERRATA_A77_1925769
sysreg_bit_set CORTEX_A77_CPUECTLR_EL1, CORTEX_A77_CPUECTLR_EL1_BIT_8
workaround_reset_end cortex_a77, ERRATUM(1925769)

check_erratum_ls cortex_a77, ERRATUM(1925769), CPU_REV(1, 1)

Note, that the long comment on every mitigation is missing. This is on
purpose, as this new format includes all of its contents into an easily
readable format.

The workaround wrappers add an erratum entry (24 bytes) to a per-cpu
data structure which can then be read by a standard reset function to
apply all errata automatically. This has the added benefit of collecting
all errata TF-A knows about in a central way, which was previously
missing. This can then be used at runtime with the errata ABI.

If an erratum doesn't fit this standard definition (eg. the
CVE_2022_23960), it can progressively be unwrapped to the old
convention. The only differences are that the naming format is slightly
more verbose and a call to add_erratum_entry is needed to inform the
framework about the errata.

Finally, the internal workaround names change a tiny bit, especially
CVEs.

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: Iac644f85dcf85b8279b25e83baf1e7d08b253b16

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refactor(cpus): convert print_errata_status to C

The function is called in a fully initialised C environment and calls
into other C functions. The Aarch differences are minimal and are hidden
by the

refactor(cpus): convert print_errata_status to C

The function is called in a fully initialised C environment and calls
into other C functions. The Aarch differences are minimal and are hidden
by the pre-existing headers. Converting it results into cleaner code
that is the same across both Aarch64 and Aarch32.

To avoid having to do very ugly pointer arithmetic, define a C struct
for the cpu_ops for both Aarch64 and Aarch32.

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: Idc07c4064e03143c88a4a0e2d10ceda70ba19a50

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refactor(cpus): rename errata_report.h to errata.h

The ERRATA_XXX macros, used in cpu_helpers.S, are necessary for the
check_errata_xxx family of functions. The CPU_REV should be used in the
cpu fil

refactor(cpus): rename errata_report.h to errata.h

The ERRATA_XXX macros, used in cpu_helpers.S, are necessary for the
check_errata_xxx family of functions. The CPU_REV should be used in the
cpu files but for whatever reason the values have been hard-coded so far
(at the cost of readability). It's evident this file is not strictly for
status reporting.

The new purpose of this file is to make it a one-stop-shop for all
things errata.

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: I1ce22dd36df5aa0bcfc5f2772251f91af8703dfb

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refactor(cpus): move cpu_ops field defines to a header

The cpu_macros.S file is loaded with lots of definitions for the cpu_ops
structure. However, since they are defined as .equ directives they are

refactor(cpus): move cpu_ops field defines to a header

The cpu_macros.S file is loaded with lots of definitions for the cpu_ops
structure. However, since they are defined as .equ directives they are
inaccessible for C code. Convert them to #defines, put them into order,
refactor them for readability, and extract them to a separate file to
make this possible.

This has the benefit of removing some Aarch differences and a lot of
duplicate code.

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: I72861794b6c9131285a9297d5918822ed718b228

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Merge "fix(zynqmp): handling of type el3 interrrupts" into integration

feat(fvp): mock support for CCA NV ctr

AEM FVP does not have a third CCA NV counter so the
implementation will fake it by returning the Trusted
NV counter value when the caller requests the CCA NV
c

feat(fvp): mock support for CCA NV ctr

AEM FVP does not have a third CCA NV counter so the
implementation will fake it by returning the Trusted
NV counter value when the caller requests the CCA NV
counter. This allows us to use the CCA CoT on AEM FVP
nonetheless.

The FVP platform port now gets its own version of
plat_get_nv_ctr() as it now need to diverge from the
common implementation provided at the Arm development
platforms level.

Change-Id: I3258f837249a539d943d6d783406ba222bd4554e
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>

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feat(auth): add CCA NV ctr to CCA CoT

Modifying the CCA CoT description to put the CCA content certificate
under the new CCA NV counter.

Change-Id: Ib962cef5eaa15bb9ccce86012f21327d29d4adad
Signed-

feat(auth): add CCA NV ctr to CCA CoT

Modifying the CCA CoT description to put the CCA content certificate
under the new CCA NV counter.

Change-Id: Ib962cef5eaa15bb9ccce86012f21327d29d4adad
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>

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feat(build): pass CCA NV ctr option to cert_create

Modifying build system to pass the new CCA NV counter options
ccafw_nvctr to cert_create tool in context of CCA COT

Change-Id: I9de2cdc041d96bc19

feat(build): pass CCA NV ctr option to cert_create

Modifying build system to pass the new CCA NV counter options
ccafw_nvctr to cert_create tool in context of CCA COT

Change-Id: I9de2cdc041d96bc19180c3189628ed23e68a992b
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>

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feat(cert-create): add new option for CCA NV ctr

Extends cert_create tool with a new option for CCA NV
counter: ccafw_nvctr.

And changes the non-volatile counter used to protect
the CCA Content Cer

feat(cert-create): add new option for CCA NV ctr

Extends cert_create tool with a new option for CCA NV
counter: ccafw_nvctr.

And changes the non-volatile counter used to protect
the CCA Content Certificate from the Trusted FW NV counter
to the CCA FW NV counter in the CCA CoT description.

Change-Id: I27f3ab2e25809f0dcc56fa05e5c3a25a2e861ef6
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>

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Merge "fix(tsp): flush uart console" into integration

Merge changes I31ec0001,Ib06cd024,I7c11f15d,Ie0d5d4c8,I285f3b59, ... into integration

* changes:
fix(el3-spmc): correctly account for emad_offset
refactor(el3-spmc): avoid unnecessarily revalida

Merge changes I31ec0001,Ib06cd024,I7c11f15d,Ie0d5d4c8,I285f3b59, ... into integration

* changes:
fix(el3-spmc): correctly account for emad_offset
refactor(el3-spmc): avoid unnecessarily revalidating offset
fix(el3-spmc): only call spmc_shm_check_obj() on complete objects
refactor(spmc): assert on out-of-bounds emad access
refactor(el3-spmc): spmc_shmem_obj_get_emad() will never fail
fix(el3-spmc): validate descriptor headers
fix(el3-spmc): use version-dependent minimum descriptor length
refactor(el3-spmc): check emad_count offset

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fix(build): include Cortex-A78AE cpu file for FVP

So far, the FVP platform.mk file did not include the corresponding file
for Cortex-A78AE, causing the FVP to hang when executing the
plat_reset_hand

fix(build): include Cortex-A78AE cpu file for FVP

So far, the FVP platform.mk file did not include the corresponding file
for Cortex-A78AE, causing the FVP to hang when executing the
plat_reset_handler function. The file is now included to address the
problem and to allow the new CI config for Cortex-A78AE to work
properly.

Change-Id: I8dd460831b354d8ca54841d5561df40ff193ee06
Signed-off-by: Juan Pablo Conde <juanpablo.conde@arm.com>

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Merge changes from topic "xlnx_smcc_soc_id" into integration

* changes:
feat(versal-net): add support for SMCC ARCH SOC ID
feat(versal): add support for SMCC ARCH SOC ID
refactor(versal-net):

Merge changes from topic "xlnx_smcc_soc_id" into integration

* changes:
feat(versal-net): add support for SMCC ARCH SOC ID
feat(versal): add support for SMCC ARCH SOC ID
refactor(versal-net): move macros to common header
feat(xilinx): add support to get chipid

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Merge "fix(zynqmp): make zynqmp_devices structure smaller" into integration

fix(zynqmp): make zynqmp_devices structure smaller

Pack the structure and make id/ver smaller and sorted.
The change saves 400bytes in RODATA section.

Change-Id: I8bcbe8fd589ba193551a0dd2cd19572516

fix(zynqmp): make zynqmp_devices structure smaller

Pack the structure and make id/ver smaller and sorted.
The change saves 400bytes in RODATA section.

Change-Id: I8bcbe8fd589ba193551a0dd2cd19572516252e73
Signed-off-by: Michal Simek <michal.simek@amd.com>

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Merge "fix(brcm): fix misspelled header inclusion guard" into integration

Merge changes from topic "xilinx-ipi" into integration

* changes:
feat(xilinx): fix IPI calculation for Versal/NET
feat(xilinx): setup local/remote id in header
feat(xilinx): clean macro names

Merge changes from topic "xilinx-ipi" into integration

* changes:
feat(xilinx): fix IPI calculation for Versal/NET
feat(xilinx): setup local/remote id in header
feat(xilinx): clean macro names
fix(zynqmp): do not export apu_ipi
fix(zynqmp): remove unused headers
feat(xilinx): move IPI related macros to plat_ipi.h

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Merge "feat(versal-net): add the IPI CRC checksum macro support" into integration

Merge "feat(rme): save PAuth context when RME is enabled" into integration

feat(versal-net): add support for SMCC ARCH SOC ID

Add support for SMCCC_ARCH_SOC_ID as per SMC Calling Convention for
Versal NET platform.
The SMCC ARCH SOC ID call is used by system software to ob

feat(versal-net): add support for SMCC ARCH SOC ID

Add support for SMCCC_ARCH_SOC_ID as per SMC Calling Convention for
Versal NET platform.
The SMCC ARCH SOC ID call is used by system software to obtain the SiP
defined SoC identification details.

Change-Id: I6648051c7f5fa27d2f02080209da36ee8d5a9d95
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>

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