| 6e26ffc0 | 11-Jul-2023 |
Manish V Badarkhe <manish.badarkhe@arm.com> |
Merge "docs(morello): update the boot sequence according to the TBBR boot flow" into integration |
| cd1838cc | 11-Jul-2023 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Merge "fix(intel): resolved coverity checking" into integration |
| 13fc020d | 03-Jul-2023 |
Deepthi Peter <deepthi.peter@arm.com> |
docs(morello): update the boot sequence according to the TBBR boot flow
The boot sequence mentioned in the documentation referred to an older
boot flow. This patch updates the boot sequence to the T
docs(morello): update the boot sequence according to the TBBR boot flow
The boot sequence mentioned in the documentation referred to an older
boot flow. This patch updates the boot sequence to the TBBR boot flow
that is currently being followed.
Signed-off-by: Deepthi Peter <deepthi.peter@arm.com>
Change-Id: I183458cea6d43dcf8acba2e0422920ab5541fdfc
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| 21fcd9f4 | 10-Jul-2023 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge changes from topic "psci-osi" into integration
* changes:
fix(sc7280): update system suspend in OS-initiated mode
fix(fvp): update system suspend in OS-initiated mode |
| 0a9270ab | 28-Jun-2023 |
Wing Li <wingers@google.com> |
fix(sc7280): update system suspend in OS-initiated mode
This patch fixes system suspend in OS-initiated mode by setting the
value of `last_at_pwrlvl` in the `psci_power_state_t` object to
`PLAT_MAX_
fix(sc7280): update system suspend in OS-initiated mode
This patch fixes system suspend in OS-initiated mode by setting the
value of `last_at_pwrlvl` in the `psci_power_state_t` object to
`PLAT_MAX_PWR_LVL`, which otherwise would result in undefined behavior.
This is conditionally compiled into the build depending on the value of
the `PSCI_OS_INIT_MODE` build option.
Change-Id: Ib9ff606b7eebd8a8224891a0d239a4e13311fe2a
Signed-off-by: Wing Li <wingers@google.com>
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|
| e0ef05bb | 28-Jun-2023 |
Wing Li <wingers@google.com> |
fix(fvp): update system suspend in OS-initiated mode
This patch fixes system suspend in OS-initiated mode by setting the
value of `last_at_pwrlvl` in the `psci_power_state_t` object to
`PLAT_MAX_PWR
fix(fvp): update system suspend in OS-initiated mode
This patch fixes system suspend in OS-initiated mode by setting the
value of `last_at_pwrlvl` in the `psci_power_state_t` object to
`PLAT_MAX_PWR_LVL`, which otherwise would result in undefined behavior.
This is conditionally compiled into the build depending on the value of
the `PSCI_OS_INIT_MODE` build option.
Change-Id: Ia0fb1e68af9320370325642b17c4569e9580aa3a
Signed-off-by: Wing Li <wingers@google.com>
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|
| e2ca9af1 | 10-Jul-2023 |
Lauren Wehrmeister <lauren.wehrmeister@arm.com> |
Merge changes from topic "kc/errata_refactor" into integration
* changes:
refactor(cpus): convert the Cortex-A75 to use cpu helpers
refactor(cpus): convert the Cortex-A75 to use the errata frame
Merge changes from topic "kc/errata_refactor" into integration
* changes:
refactor(cpus): convert the Cortex-A75 to use cpu helpers
refactor(cpus): convert the Cortex-A75 to use the errata framework
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|
| 1af7bf71 | 07-Jul-2023 |
Sieu Mun Tang <sieu.mun.tang@intel.com> |
fix(intel): resolved coverity checking
Coverity checking fix. Resolved unused value, deadcode and uninit.
1. CID: 395326
2. CID: 395327
3. CID: 395328
4. CID: 395329
5. CID: 395330
Signed-off
fix(intel): resolved coverity checking
Coverity checking fix. Resolved unused value, deadcode and uninit.
1. CID: 395326
2. CID: 395327
3. CID: 395328
4. CID: 395329
5. CID: 395330
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: I86b8af28dc345542b142ce53e1935bb855888238
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|
| 1eb5e903 | 10-Jul-2023 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Merge "fix(rcar): add mandatory fields in 'reserved-memory' node" into integration |
| 49c7a264 | 10-Jul-2023 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes from topic "mb/mb-design" into integration
* changes:
docs: remove redundant Measured Boot interface info
docs: add Measured Boot design |
| bd596a10 | 06-Jul-2023 |
Govindraj Raja <govindraj.raja@arm.com> |
build(fpga): remove a710 from fpga build
Currently we have a large series of errata_refactor patches pending
and they are all failing on arm_fpga build when we add errata_framework.
Errata framewor
build(fpga): remove a710 from fpga build
Currently we have a large series of errata_refactor patches pending
and they are all failing on arm_fpga build when we add errata_framework.
Errata framework can cause the size to grow and thus causing build
failure on bl31 size. This as of today is blocking us from
merging most of our changes as it will introduce a CI failure.
As an workaround we try to just reduce the arm_fpga build by a710
platform, we have a715 and a720 which should be ok I think.
Once everyone are available for further discussion we could revert this
change back and discuss further whats the right approach.
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
Change-Id: I96a821e10aaecf04db7407fb2df38012839bfb94
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|
| e318411f | 07-Jul-2023 |
Olivier Deprez <olivier.deprez@arm.com> |
Merge "docs: add guidelines for abandoning patches" into integration |
| 3393060c | 06-Jul-2023 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes from topic "agilex5" into integration
* changes:
feat(intel): platform enablement for Agilex5 SoC FPGA
feat(intel): ccu driver for Agilex5 SoC FPGA
feat(intel): vab support for A
Merge changes from topic "agilex5" into integration
* changes:
feat(intel): platform enablement for Agilex5 SoC FPGA
feat(intel): ccu driver for Agilex5 SoC FPGA
feat(intel): vab support for Agilex5 SoC FPGA
feat(intel): sdmmc/nand/combo-phy/qspi driver for Agilex5 SoC FPGA
feat(intel): ddr driver for Agilex5 SoC FPGA
feat(intel): power manager for Agilex5 SoC FPGA
feat(intel): cold/warm reset and smp support for Agilex5 SoC FPGA
feat(intel): reset manager support for Agilex5 SoC FPGA
feat(intel): mailbox and SMC support for Agilex5 SoC FPGA
feat(intel): system manager support for Agilex5 SoC FPGA
feat(intel): memory controller support for Agilex5 SoC FPGA
feat(intel): clock manager support for Agilex5 SoC FPGA
feat(intel): mmc support for Agilex5 SoC FPGA
feat(intel): uart support for Agilex5 SoC FPGA
feat(intel): pinmux, peripheral and Handoff support for Agilex5 SoC FPGA
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| 0e74b661 | 06-Jul-2023 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes from topic "imx93_basic_support" into integration
* changes:
docs(imx9): add imx93 platform
feat(imx93): add OPTEE support
feat(imx93): protect OPTEE memory to secure access only
Merge changes from topic "imx93_basic_support" into integration
* changes:
docs(imx9): add imx93 platform
feat(imx93): add OPTEE support
feat(imx93): protect OPTEE memory to secure access only
feat(imx93): add cpuidle and basic suspend support
feat(imx93): add reset & poweroff support
feat(imx93): allow SoC masters access to system TCM
feat(imx93): update the ocram trdc config for did10
feat(imx93): add the basic support
feat(imx93): add the trdc driver
build(changelog): add new scopes for nxp imx platform
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|
| 74599321 | 06-Jul-2023 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "feat(qemu): add "neoverse-v1" cpu support" into integration |
| a1c93550 | 15-Jun-2023 |
Manish V Badarkhe <Manish.Badarkhe@arm.com> |
docs: remove redundant Measured Boot interface info
A separate design document for Measured Boot covers the porting
guidelines for the Measured Boot interfaces. As a result,
the Measured Boot interf
docs: remove redundant Measured Boot interface info
A separate design document for Measured Boot covers the porting
guidelines for the Measured Boot interfaces. As a result,
the Measured Boot interfaces have been removed from the porting
guide and a link to the Measured Boot design document has been
provided.
Change-Id: Ia6bd2620d830aea6aececab4af7e10a6d737f025
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
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|
| 5038f1f9 | 12-Jun-2023 |
Manish V Badarkhe <Manish.Badarkhe@arm.com> |
docs: add Measured Boot design
Added design document for Measured Boot implementation in
TF-A.
Change-Id: I25b57ec555b289eb6bbf0a6aae014d7bf6d152fd
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe
docs: add Measured Boot design
Added design document for Measured Boot implementation in
TF-A.
Change-Id: I25b57ec555b289eb6bbf0a6aae014d7bf6d152fd
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
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|
| 8671000f | 04-Jul-2023 |
Manish V Badarkhe <Manish.Badarkhe@arm.com> |
docs: add guidelines for abandoning patches
The code review guidelines have been updated to explain when
patches that do not receive a response to the review comments
will be abandoned.
Change-Id:
docs: add guidelines for abandoning patches
The code review guidelines have been updated to explain when
patches that do not receive a response to the review comments
will be abandoned.
Change-Id: I60539e16ca41245cf1b352f24557be1b3c67c367
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
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|
| 2f3780e3 | 06-Jul-2023 |
Manish V Badarkhe <manish.badarkhe@arm.com> |
Merge "feat(build): march option selection" into integration |
| da36a232 | 06-Jul-2023 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Merge changes from topic "mb/mb-rss-refactor" into integration
* changes:
refactor(tc): update RSS driver inteface calls
refactor(fvp): update RSS driver inteface calls
refactor(rss): make RSS
Merge changes from topic "mb/mb-rss-refactor" into integration
* changes:
refactor(tc): update RSS driver inteface calls
refactor(fvp): update RSS driver inteface calls
refactor(rss): make RSS driver standalone for Measured Boot
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|
| 1fc20d7f | 30-Jun-2023 |
Jimmy Brisson <jimmy.brisson@arm.com> |
fix(tc): rename macro to match PSA spec
Update 'PSA_INITIAL_ATTEST_TOKEN_MAX_SIZE' to
'PSA_INITIAL_ATTEST_MAX_TOKEN_SIZE' which is defined
in the PSA Certified Attestation API spec.
Change-Id: I583
fix(tc): rename macro to match PSA spec
Update 'PSA_INITIAL_ATTEST_TOKEN_MAX_SIZE' to
'PSA_INITIAL_ATTEST_MAX_TOKEN_SIZE' which is defined
in the PSA Certified Attestation API spec.
Change-Id: I5837fea552e6fe18a203412eb90d41e2f90ad6f1
Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>
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| b0542b58 | 04-Jul-2023 |
Jimmy Brisson <jimmy.brisson@arm.com> |
fix(tc): Correct return type
The fact that this was void instead of int, as required, caused
the test-running code to assume that the tests always failed.
Fixing the return type fixes the always-te
fix(tc): Correct return type
The fact that this was void instead of int, as required, caused
the test-running code to assume that the tests always failed.
Fixing the return type fixes the always-tests-failing bug.
Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>
Change-Id: Ief55fe15c437c87dac1d03419a8e148f5d864b8d
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| 0e04a201 | 05-Jul-2023 |
Olivier Deprez <olivier.deprez@arm.com> |
Merge "build(tools): avoid unnecessary link" into integration |
| aa57ce63 | 04-Jul-2023 |
Vincent Stehlé <vincent.stehle@arm.com> |
build(tools): avoid unnecessary link
In their respective makefiles, cert_create, encrypt_fw and fiptool
depend on the --openssl phony target as a prerequisite. This forces
those tools to be re-linke
build(tools): avoid unnecessary link
In their respective makefiles, cert_create, encrypt_fw and fiptool
depend on the --openssl phony target as a prerequisite. This forces
those tools to be re-linked each time.
Move the dependencies on the --openssl target from the tools to their
makefiles all targets, to avoid unnecessary linking while preserving the
OpenSSL version printing done in the --openssl targets when in debug.
Fixes: cf2dd17ddda2 ("refactor(security): add OpenSSL 1.x compatibility")
Signed-off-by: Vincent Stehlé <vincent.stehle@arm.com>
Change-Id: I98a3ab30f36dffc253cecaaf3a57d2712522135d
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| e69400cf | 05-Jul-2023 |
Manish V Badarkhe <manish.badarkhe@arm.com> |
Merge "feat(morello): fdts: add CoreSight DeviceTree bindings" into integration |