feat(fvp): add mbedtls_asn1_get_len symbol in ROMlib

mbedtls_asn1_get_len() will be needed by the X.509 parser in an
upcoming patch.

Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Cha

feat(fvp): add mbedtls_asn1_get_len symbol in ROMlib

mbedtls_asn1_get_len() will be needed by the X.509 parser in an
upcoming patch.

Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Change-Id: I14310c80033a1142a94c0c4b54d63331479b643d

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fix(cpus): reduce generic_errata_report()'s size

For a pretty implementation and straightforward code, the CVE/erratum
dispatching of the errata status reporting was done with a macro,
closely follo

fix(cpus): reduce generic_errata_report()'s size

For a pretty implementation and straightforward code, the CVE/erratum
dispatching of the errata status reporting was done with a macro,
closely following the old code. Unfortunately, this produces a function
that was over a kilobyte in size, which unsurprisingly doesn't fit on
some platforms.

Convert the macro to a proper C function and call it once. Also hide the
errata ordering checking behind the FEATURE_DETECTION flag to further
save space. This functionality is not necessary for most builds.
Development and platform bringup builds, which should find this
functionality useful, are expected to have FEATURE_DETECTION enabled.

This reduces the function to under 600 bytes.

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: Ibf5376a26cbae28d9dc010128452cb3c694a3f78

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feat(cpus): add more errata framework helpers

Figuring out the naming format of errata is annoying, so add a shorthand
for the custom checker functions. Also add some more semantic macros
instead of

feat(cpus): add more errata framework helpers

Figuring out the naming format of errata is annoying, so add a shorthand
for the custom checker functions. Also add some more semantic macros
instead of passing around constants.

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: Ibdcf72146738026df4ebd047bfb30790fd4a1053

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docs: document the errata framework

Also add a recommended Procedure Call Standard (PCS) to use inside CPU
files and split everything into sections to make it easier to follow.

Signed-off-by: Boyan

docs: document the errata framework

Also add a recommended Procedure Call Standard (PCS) to use inside CPU
files and split everything into sections to make it easier to follow.

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: Idd876d8e598b5dfe1193aa3e7375c52f6edf5671

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Merge "feat(ast2700): add Aspeed AST2700 platform support" into integration

docs: update PSCI reference

PSCI specification reference in the documentation is updated
to point to latest specification and duplicate PSCI references are
removed.

Change-Id: I35ee365f08c557f3017a

docs: update PSCI reference

PSCI specification reference in the documentation is updated
to point to latest specification and duplicate PSCI references are
removed.

Change-Id: I35ee365f08c557f3017af4d51f6d063a7501b27e
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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Merge "fix(spmd): relax use of EHF with SPMC at S-EL2" into integration

Merge "fix(versal): add missing irq mapping for wakeup src" into integration

feat(intel): add intel_rsu_update() to sip_svc_v2

Add smc function id for intel_rsu_update() in sip_svc_v2. For temporarily
saving the RSU application image address before a cold reset is
issued.

S

feat(intel): add intel_rsu_update() to sip_svc_v2

Add smc function id for intel_rsu_update() in sip_svc_v2. For temporarily
saving the RSU application image address before a cold reset is
issued.

Signed-off-by: Mahesh Rao <mahesh.rao@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I43bc7bd5aa5fa9238bceba1d826bf0a34ff87adb

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fix(versal): add missing irq mapping for wakeup src

The commit 0ec6c31320c6 provides irq to device index mapping
which is required to check for IRQs and set peripheral as a
wake source if IRQ is ena

fix(versal): add missing irq mapping for wakeup src

The commit 0ec6c31320c6 provides irq to device index mapping
which is required to check for IRQs and set peripheral as a
wake source if IRQ is enabled. But in that commit some IRQ
numbers are missed. Because of that, wakeup using some
peripheral interrupts will not work. Add those missing IRQ
numbers.

Fixes: 0ec6c31320c6 ("feat(versal): replace irq array with switch case")
Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Change-Id: Icbc773050c328be253702e63e7cf8450c7dee133

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fix(spmd): relax use of EHF with SPMC at S-EL2

Follow up to [1] and [2], for systems implementing the SPMC at S-EL2,
it is necessary to leave the option for handling Group0 interrupts
(while the nor

fix(spmd): relax use of EHF with SPMC at S-EL2

Follow up to [1] and [2], for systems implementing the SPMC at S-EL2,
it is necessary to leave the option for handling Group0 interrupts
(while the normal world runs) through the EHF by the use of the
EL3_EXCEPTION_HANDLING option.
Specifically for RAS, the handling through EHF is still required because
the platform function provided by the SPMD doesn't provide the facility
to link back to the RAS handling framework.

[1] https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/16047
[2] https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/19897

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: Idf8741887904a286fb3f5ab2d754afd2fc78d3b0

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feat(lib): implement memcpy_s in lib

To support memcpy_s for better security purpose
to avoid overflowing the dest while copy from src.

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-I

feat(lib): implement memcpy_s in lib

To support memcpy_s for better security purpose
to avoid overflowing the dest while copy from src.

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I63c3ea6a3e99c10d69be6bce04843c14b0a28a4d

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Merge "docs: update Measured Boot PoC" into integration

refactor(el3-spmc): add comments

Change-Id: Ic58f4966159cafa83eec8e6b18a96b0a8b2ce781
Signed-off-by: Demi Marie Obenour <demiobenour@gmail.com>

refactor(el3-spmc): move checks after loop

This makes the code cleaner. No functional change intended.

Change-Id: Ib7b438b830e8e3b7ac6e30d688f5172cbaa58121
Signed-off-by: Demi Marie Obenour <demio

refactor(el3-spmc): move checks after loop

This makes the code cleaner. No functional change intended.

Change-Id: Ib7b438b830e8e3b7ac6e30d688f5172cbaa58121
Signed-off-by: Demi Marie Obenour <demiobenour@gmail.com>

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refactor(el3-spmc): validate alignment earlier

Future changes will cause spmc_shmem_obj_get_comp_mrd to panic instead
of returning NULL, so be sure that comp_mrd_offset has been validated
already.

refactor(el3-spmc): validate alignment earlier

Future changes will cause spmc_shmem_obj_get_comp_mrd to panic instead
of returning NULL, so be sure that comp_mrd_offset has been validated
already. The existing code checks for 8-byte alignment, but comments in
el3_spmc_ffa_memory.h indicate that 16-byte alignment is expected, so
require 16-byte alignment.

Change-Id: I400f0f1f163522cb5ea77d4811c91e8b7e655c18
Signed-off-by: Demi Marie Obenour <demiobenour@gmail.com>

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Merge "fix(zynqmp): fix prepare_dtb() memory description" into integration

Merge "chore(bl): add UNALIGNED symbols for TEXT/RODATA" into integration

Merge changes from topics "hm/latex", "hm/latexpdf" into integration

* changes:
fix(docs): fix build errors for latexpdf
chore: reformat sphinx configuration

chore(bl): add UNALIGNED symbols for TEXT/RODATA

Add symbols to mark end of TEXT/RODATA before page alignment.
Similar change was done by commit 8d69a03f6a7d ("Various
improvements/cleanups on the l

chore(bl): add UNALIGNED symbols for TEXT/RODATA

Add symbols to mark end of TEXT/RODATA before page alignment.
Similar change was done by commit 8d69a03f6a7d ("Various
improvements/cleanups on the linker scripts") for
RO_END/COHERENT_RAM. These symbols help to know how much free
space is in the final binary because of page alignment.

Also show all *UNALIGNED__ symbols via poetry.
For example:
poetry run memory -p zynqmp -b debug

Change-Id: I322beba37dad76be9f4e88ca7e5b3eff2df7d96e
Signed-off-by: Michal Simek <michal.simek@amd.com>

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fix(docs): fix build errors for latexpdf

Fixes errors encountered when handling SVG graphics, unicode characters,
and deeply nested lists (i.e. in the change log) with the `latexpdf`
docs build. Add

fix(docs): fix build errors for latexpdf

Fixes errors encountered when handling SVG graphics, unicode characters,
and deeply nested lists (i.e. in the change log) with the `latexpdf`
docs build. Adds `sphinxcontrib-svg2pdfconverter` to allow embedding SVG
images into PDF files; changes the LaTeX engine to XeLaTex to provide
wider support for unicode characters (see [1] for more details); and
increases the maximum list depth.

[1] https://www.sphinx-doc.org/en/master/usage/configuration.html#confval-latex_engine

Change-Id: I2ee265d301f6822bae7aa6dfa3a8bfcf070076d3
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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Merge changes from topic "psci-osi" into integration

* changes:
fix(psci): add optional pwr_domain_validate_suspend to plat_psci_ops_t
fix(sc7280): update pwr_domain_suspend
fix(fvp): update p

Merge changes from topic "psci-osi" into integration

* changes:
fix(psci): add optional pwr_domain_validate_suspend to plat_psci_ops_t
fix(sc7280): update pwr_domain_suspend
fix(fvp): update pwr_domain_suspend

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docs: update Measured Boot PoC

Updated the Measured Boot PoC to be compliant with the current TF-A
implementation that supports multiple Measured Boot backends, which
are the RSS and Event Log.

Cha

docs: update Measured Boot PoC

Updated the Measured Boot PoC to be compliant with the current TF-A
implementation that supports multiple Measured Boot backends, which
are the RSS and Event Log.

Change-Id: I8a38a801dd75e6282d103e154966959bba2d1ec7
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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Merge "fix(memmap): reintroduce support for GNU map files" into integration

feat(ast2700): add Aspeed AST2700 platform support

Aspeed AST2700 is a quad-core SoC with ARM Cortex-A35 integrated.
This patch adds the initial platform support for AST2700 and also
updates the doc

feat(ast2700): add Aspeed AST2700 platform support

Aspeed AST2700 is a quad-core SoC with ARM Cortex-A35 integrated.
This patch adds the initial platform support for AST2700 and also
updates the documents.

Change-Id: I1796f7aae5ed2d1799e91fabb8949607959cd9b3
Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>

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