Merge changes Ic58f4966,Ib7b438b8,I400f0f1f into integration

* changes:
refactor(el3-spmc): add comments
refactor(el3-spmc): move checks after loop
refactor(el3-spmc): validate alignment earli

Merge changes Ic58f4966,Ib7b438b8,I400f0f1f into integration

* changes:
refactor(el3-spmc): add comments
refactor(el3-spmc): move checks after loop
refactor(el3-spmc): validate alignment earlier

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Merge "feat(intel): add intel_rsu_update() to sip_svc_v2" into integration

Merge "feat(lib): implement memcpy_s in lib" into integration

fix(zynqmp): type cast addresses to fix overflow issue

Type cast the build time base and size argument to unsigned integer
and the limit derived from these two as unsigned long to avoid
size overflo

fix(zynqmp): type cast addresses to fix overflow issue

Type cast the build time base and size argument to unsigned integer
and the limit derived from these two as unsigned long to avoid
size overflow issue during build.

For zynqmp platform, calculating the limit without typecasting results
in build error as follows

make -j DEBUG=0 RESET_TO_BL31=1 PLAT=zynqmp \
ZYNQMP_ATF_MEM_BASE=0x70000000 ZYNQMP_ATF_MEM_SIZE=0x10000000 \
XILINX_OF_BOARD_DTB_ADDR=0x100000 bl31

plat/xilinx/zynqmp/include/platform_def.h:51:62:
error: integer overflow in expression of type 'int' results
in '-2147483648' [-Werror=overflow]
51 | # define BL31_LIMIT (ZYNQMP_ATF_MEM_BASE + ZYNQMP_ATF_MEM_SIZE)

Change-Id: Id093a50e748884d4fba65626e94f361f6c23cecc
Signed-off-by: Michal Simek <michal.simek@amd.com>
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>

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fix: integer suffix macro definition

The current implementation of macro L/LL/UL/ULL concatenates the input
with "L"/"LL"/"UL"/"ULL" respectively.
In the case where a macro is passed to L/LL/UL/ULL

fix: integer suffix macro definition

The current implementation of macro L/LL/UL/ULL concatenates the input
with "L"/"LL"/"UL"/"ULL" respectively.
In the case where a macro is passed to L/LL/UL/ULL as input,
the input macro name is concatenated with, rather than expanding
the input macro and then concatenating it.
The implementation of L/LL/UL/ULL is modified to two level macro,
so as to concatenate to the expansion of a macro argument.

Change 5b33ad174a0 "Unify type of "cpu_idx" across PSCI module."
has modified the implementation of U() to two level macros without
changing the implementation of other macros.

Change-Id: Ie93d67dff5ce96223a3faf6c98b98fcda530fc34
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>

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Merge "build(changelog): pretend scope-less `build` changes have the `build` scope" into integration

Merge changes from topic "jc/refact_Makefile" into integration

* changes:
refactor(build): move SVE_VECTOR_LEN flag to add_defines section
refactor(build): cleanup Makefile to handle build flags

Merge changes from topic "jc/refact_Makefile" into integration

* changes:
refactor(build): move SVE_VECTOR_LEN flag to add_defines section
refactor(build): cleanup Makefile to handle build flags precisely

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Merge "fix: pass SMCCCv1.3 SVE hint to internal flags" into integration

Merge changes I814cdadb,I429eb473,I441f9a60 into integration

* changes:
fix(n1sdp): fix spi_ids range for n1sdp multichip boot
fix(gicv3): move invocation of gicv3_get_multichip_base function

Merge changes I814cdadb,I429eb473,I441f9a60 into integration

* changes:
fix(n1sdp): fix spi_ids range for n1sdp multichip boot
fix(gicv3): move invocation of gicv3_get_multichip_base function
fix(gic600): fix gic600 maximum SPI ID

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refactor(build): move SVE_VECTOR_LEN flag to add_defines section

Presently, we have an explicit section to add definitions, wherein
we evaluate the definitions after being overwritten by the platfor

refactor(build): move SVE_VECTOR_LEN flag to add_defines section

Presently, we have an explicit section to add definitions, wherein
we evaluate the definitions after being overwritten by the platform.

To keep it aligned with this pattern, SVE_VECTOR_LEN is moved here.

Change-Id: Ia3373d954a7ee97980fe72d5a069e202352f25b1
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>

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refactor(build): cleanup Makefile to handle build flags precisely

Presently, Makefile is unsystematic with no precise ordering
of configuration and commands.
This patch addresses this issue, by sort

refactor(build): cleanup Makefile to handle build flags precisely

Presently, Makefile is unsystematic with no precise ordering
of configuration and commands.
This patch addresses this issue, by sorting and arranging the related
sections in an order, which helps in maintaining it precisely.
Further, this assists developers in identifying the concerned section
and add related changes appropriately with ease.

Additionally, SIMICS build option linked to Intel platform, has been
removed, as there is no platform specific support to utilise it.
[https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/16737]

Change-Id: I72c09905334f94f803cdfd85f56e2c9572f9b3ef
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>

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fix(n1sdp): fix spi_ids range for n1sdp multichip boot

According to GIC-600 TRM, it supports upto 960 SPIs.
This patch configures the SPI IDs range to 32-991, and distributes
them equally across bot

fix(n1sdp): fix spi_ids range for n1sdp multichip boot

According to GIC-600 TRM, it supports upto 960 SPIs.
This patch configures the SPI IDs range to 32-991, and distributes
them equally across both the chips.

Signed-off-by: sahil <sahil@arm.com>
Change-Id: I814cdadb59c8765c239ae0375e547718b7f208ff

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Merge changes from topic "fix-for-hash-lengths" into integration

* changes:
fix(auth): allow hashes of different lengths
feat(juno): add mbedtls_asn1_get_len symbol in ROMlib
feat(fvp): add mb

Merge changes from topic "fix-for-hash-lengths" into integration

* changes:
fix(auth): allow hashes of different lengths
feat(juno): add mbedtls_asn1_get_len symbol in ROMlib
feat(fvp): add mbedtls_asn1_get_len symbol in ROMlib

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refactor(cpus): convert Cortex-A715 to the errata framework

This involves replacing:
* the reset_func with the standard cpu_reset_func_{start,end} to apply
errata automatically
* the <cpu>_erra

refactor(cpus): convert Cortex-A715 to the errata framework

This involves replacing:
* the reset_func with the standard cpu_reset_func_{start,end} to apply
errata automatically
* the <cpu>_errata_report with the errata_report_shim to report errata
automatically
...and for each erratum:
* the prologue with the workaround_<type>_start to do the checks and
framework registration automatically
* the epilogue with the workaround_<type>_end
* the checker function with the check_erratum_<type> to make it more
descriptive

It is important to note that the errata workaround and checking
sequences remain unchanged and preserve their git blame. Testing was
conducted by:

* Building for release with all errata flags enabled and running script
in change 19136 to compare output of objdump for each errata.
* Manual comparison of disassembly of converted functions with non-
converted functions
* Build for debug with all errata enabled and step through ArmDS
at reset to ensure all functions are entered.

Change-Id: Ib63b6310997d523fa8bd7f867e53fedec66f1e06
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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feat(plat/qemu): add sdei support for QEMU

Add sdei support for QEMU, this is to let jailhouse Hypervisor
use SDEI to do hypervisor management, after physical IRQ
has been disabled routing.

Note: T

feat(plat/qemu): add sdei support for QEMU

Add sdei support for QEMU, this is to let jailhouse Hypervisor
use SDEI to do hypervisor management, after physical IRQ
has been disabled routing.

Note: To enable SDEI in QEMU, it needs to set "SDEI_SUPPORT=1
EL3_EXCEPTION_HANDLING=1" when compiling.

Signed-off-by: Dongjiu Geng <gengdongjiu1@gmail.com>
Change-Id: Ia7f9c5a0db36da03e5c6e6fb1270281f19924d77

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Merge "chore(smccc): bump up SMCCC version to 1.4" into integration

fix: pass SMCCCv1.3 SVE hint to internal flags

This change fixes the initial support for SMCCCv1.3 SVE hint bit [1].
In the aarch64 smc handler, the FID[16] bit is improperly extracted
and results i

fix: pass SMCCCv1.3 SVE hint to internal flags

This change fixes the initial support for SMCCCv1.3 SVE hint bit [1].
In the aarch64 smc handler, the FID[16] bit is improperly extracted
and results in the corresponding flags bit to be always set.
Fix by doing the proper masking and set into the flags register.

[1] https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/17511

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I62b8e211d48a50f28e184ff27cd718f51d8d56bf

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chore(smccc): bump up SMCCC version to 1.4

TF-A code supports SMCCC spec version 1.4 while version is still kept
1.2. Bump up the version.

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Chan

chore(smccc): bump up SMCCC version to 1.4

TF-A code supports SMCCC spec version 1.4 while version is still kept
1.2. Bump up the version.

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: Ie5476c4601bd504d3f3e8433e1d672ebd0a758b1

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fix(gicv3): move invocation of gicv3_get_multichip_base function

gicv3_get_multichip_base in case of GICV3_IMPL_GIC600_MULTICHIP flag
being set, only works if the id belongs to SPI range.
Moving inv

fix(gicv3): move invocation of gicv3_get_multichip_base function

gicv3_get_multichip_base in case of GICV3_IMPL_GIC600_MULTICHIP flag
being set, only works if the id belongs to SPI range.
Moving invocation of the function after confirming that the
intr_num belongs to SPI range.

Signed-off-by: sahil <sahil@arm.com>
Change-Id: I429eb473a7aeccb30309b1ffa5994663393ba0a2

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fix(gic600): fix gic600 maximum SPI ID

According to GIC-600 TRM, it supports up to 960 SPIs. With the
starting SPI_ID of 32, the maximum SPI_ID should be 991. This patch
fixes the value of GIC600_SP

fix(gic600): fix gic600 maximum SPI ID

According to GIC-600 TRM, it supports up to 960 SPIs. With the
starting SPI_ID of 32, the maximum SPI_ID should be 991. This patch
fixes the value of GIC600_SPI_ID_MAX which is currently configured
to be 960.

Signed-off-by: sahil <sahil@arm.com>
Change-Id: I441f9a607d160db8533f2a03e02afd1a9bab991e

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Merge "docs: update PSCI reference" into integration

Merge "fix(cpus): reduce generic_errata_report()'s size" into integration

Merge changes from topic "bk/errata_refactor" into integration

* changes:
feat(cpus): add more errata framework helpers
docs: document the errata framework

fix(auth): allow hashes of different lengths

Trusted Board Boot supports multiple hash algorithms, including SHA-256,
SHA-384, and SHA-512. These algorithms produce hashes of different
lengths, so

fix(auth): allow hashes of different lengths

Trusted Board Boot supports multiple hash algorithms, including SHA-256,
SHA-384, and SHA-512. These algorithms produce hashes of different
lengths, so the resulting DER-encoded hash objects are also of different
lengths. However, the common Trusted Board Boot code only stores the
contents of the object, not its length. Before commit
f47547b35462571636a76b737602e827ae43bc24, this was harmless: ASN.1
objects are self-delimiting, and any excess padding was ignored.
f47547b35462571636a76b737602e827ae43bc24 changed the code to reject
excess padding. However, this breaks using a shorter hash in a build
that supports longer hashes: the shorter hash will have padding after
it, and verify_hash() will reject it. This was found by an Arm
customer: TF-A v2.9 refused to boot, even though TF-A v2.6 (which did
not have f47547b35462571636a76b737602e827ae43bc24) worked just fine.

Storing the length of the hash turns out to be quite difficult.
However, it turns out that hashes verified by verify_hash() always come
from the ROTPK or an X.509 certificate extension. Furthermore, _all_
X.509 certificate extensions used by Trusted Board Boot are ASN.1
DER encoded, so it is possible to reject padding in get_ext(). Padding
after the ROTPK is harmless, and it is better to ignore that padding
than to refuse to boot the system.

Change-Id: I28a19d7783e6036b65e86426d78c8e5b2ed6f542
Fixes: f47547b35462571636a76b737602e827ae43bc24 ("fix(auth): reject invalid padding in digests")
Signed-off-by: Demi Marie Obenour <demiobenour@gmail.com>

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feat(juno): add mbedtls_asn1_get_len symbol in ROMlib

mbedtls_asn1_get_len() will be needed by the X.509 parser in an
upcoming patch.

Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Ch

feat(juno): add mbedtls_asn1_get_len symbol in ROMlib

mbedtls_asn1_get_len() will be needed by the X.509 parser in an
upcoming patch.

Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Change-Id: I5609da000bbfc8a1503c298550ae3b0ba881fc96

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