refactor(cpus): reorder Cortex-X1 errata by ascending order

Change-Id: I1e580dd330b545370b23d4b9704d899f6a679250
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

refactor(cpus): use cpu errata wrappers Cortex-A12 aarch32 cpu

Adapt to use errata frame-work cpu macro helpers for Cortex-A12
aarch32 cpu.

Testing:
- Manual comparison of disassembly with and with

refactor(cpus): use cpu errata wrappers Cortex-A12 aarch32 cpu

Adapt to use errata frame-work cpu macro helpers for Cortex-A12
aarch32 cpu.

Testing:
- Manual comparison of disassembly with and without the patch.
- Compile testing.

Change-Id: I9bad7f1e3d87419c0451b5d46edf0c406d31a84d
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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refactor(cpus): use cpu errata wrappers Cortex-A7 and A9 aarch32 cpus

Adapt to use errata frame-work cpu macro helpers for following cpu's:

- Cortex-A7
- Cortex-A9

Testing:
- Manual comparison of

refactor(cpus): use cpu errata wrappers Cortex-A7 and A9 aarch32 cpus

Adapt to use errata frame-work cpu macro helpers for following cpu's:

- Cortex-A7
- Cortex-A9

Testing:
- Manual comparison of disassembly with and without the patch.
- Compile testing.

Change-Id: I88eb90d7fd0e82fc4bfc9d1aee947f0c820e1222
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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Merge "fix(imx8m): make IMX_BOOT_UART_BASE autodetection option more obvious" into integration

feat(spmd): add spmd logical partitions

Add header file to help with creation of SPMD logical partitions. Also
update linker files to create sections to record SPMD logical partitions
declared. This

feat(spmd): add spmd logical partitions

Add header file to help with creation of SPMD logical partitions. Also
update linker files to create sections to record SPMD logical partitions
declared. This follows the same pattern as the EL3 SPMC's logical
partitions. This patch also adds initialization of SPMD logical
partitions when the SPMD comes up.
ENABLE_SPMD_LP is a build flag that is used to enable support for
SPMD logical partitions.
Note that the approach chosen is to keep SPMD and SPMC logical
partition support separate, as opposed to extend the existing SPMC
logical partition support since the code would need to have a number of
ifdefs and the interactions with various build options such as
SPMC_AT_EL3 needs to be accounted for, which would make code more
complicated.

Signed-off-by: Raghu Krishnamurthy <raghu.ncstate@gmail.com>
Change-Id: I9642ddbf6ea26dd3f4a283baec598d61c07e3661

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Merge "fix(xilinx): remove clock_setrate and clock_getrate api" into integration

fix(xilinx): remove clock_setrate and clock_getrate api

As per the current code base, PM_CLOCK_SETRATE and PM_CLOCK_GETRATE
APIs are not supported for the runtime operations in the firmware and
the

fix(xilinx): remove clock_setrate and clock_getrate api

As per the current code base, PM_CLOCK_SETRATE and PM_CLOCK_GETRATE
APIs are not supported for the runtime operations in the firmware and
the TF-A it is already returning an error when there is any request
to access these APIs. So, just removing the unused code to avoid the
confusion around these APIs.

Also, there is no issue with the backward compatibility as these APIs
were never used since implemented. Hence no need to bump up the
version of the feature check API as well.

Signed-off-by: Ronak Jain <ronak.jain@amd.com>
Change-Id: I444f973e62cd25aae2e7f697d808210b265106ad

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feat(cpufeat): initialize HFG*_EL2 registers

HFG*_EL2 registers control the fine-grained traps introduced by
FEAT_FGT. These traps come enabled by default so old systems unaware
of this feature can

feat(cpufeat): initialize HFG*_EL2 registers

HFG*_EL2 registers control the fine-grained traps introduced by
FEAT_FGT. These traps come enabled by default so old systems unaware
of this feature can be trapped to EL3, not being able to handle the
trap correctly. This patch disables all fine-grained traps by default
to prevent such unexpected behavior.

Change-Id: If2ae97accbeed2bea51ae03b5225ce762ecffb25
Signed-off-by: Juan Pablo Conde <juanpablo.conde@arm.com>

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docs: remove blank pages from PDF documentation

The PDF documentation download has a lot of blank pages. This is
because Sphinx starts each section on an odd numbered page for
duplex printing. This

docs: remove blank pages from PDF documentation

The PDF documentation download has a lot of blank pages. This is
because Sphinx starts each section on an odd numbered page for
duplex printing. This patch fixes this to allow sections to start
on any page.

Change-Id: I1ba8a4707c39b54205f2a3c9b47c1c21a3fedcb9
Signed-off-by: Elizabeth Ho <elizabeth.ho@arm.com>

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docs(rme): update tftf build command

Deprecate pack_realm build command for TFTF.
To build Realm payload tests use ENABLE_REALM_PAYLOAD_TESTS=1.
This new command line for TFTF is effective from SHA

docs(rme): update tftf build command

Deprecate pack_realm build command for TFTF.
To build Realm payload tests use ENABLE_REALM_PAYLOAD_TESTS=1.
This new command line for TFTF is effective from SHA 9945bef6b
in tf-a-tests repo.

Signed-off-by: Shruti Gupta <shruti.gupta@arm.com>
Change-Id: Iee9ac9b2b367aac50677fac95631e7e4818cdf3a

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fix(imx8m): make IMX_BOOT_UART_BASE autodetection option more obvious

Switch from IMX_BOOT_UART_BASE=0 to IMX_BOOT_UART_BASE=auto to make it
more obvious that the detection is based on the runtime a

fix(imx8m): make IMX_BOOT_UART_BASE autodetection option more obvious

Switch from IMX_BOOT_UART_BASE=0 to IMX_BOOT_UART_BASE=auto to make it
more obvious that the detection is based on the runtime autodetection.

In addition this moves the evaluation of IMX_BOOT_UART_BASE into the
makefile which removes the ugly conditional compilation as well.

Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
Change-Id: I92c13607bf81c6267f4b6aee829d74902b7f72d2

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Merge changes from topic "CPU_RAS_FF" into integration

* changes:
feat(rdn2): enable Neoverse N2 CPU error handling support
feat(sgi): firmware first error handling for Neoverse N2 CPU
feat(ar

Merge changes from topic "CPU_RAS_FF" into integration

* changes:
feat(rdn2): enable Neoverse N2 CPU error handling support
feat(sgi): firmware first error handling for Neoverse N2 CPU
feat(arm): enable FHI PPI interrupt to report CPU errors

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feat(rdn2): enable Neoverse N2 CPU error handling support

Defines N2 CPU RAS error for RD-N2 platform variants. Enables N2 CPU
error handling on RD-N2 platform variants.

Signed-off-by: Omkar Anand

feat(rdn2): enable Neoverse N2 CPU error handling support

Defines N2 CPU RAS error for RD-N2 platform variants. Enables N2 CPU
error handling on RD-N2 platform variants.

Signed-off-by: Omkar Anand Kulkarni <omkar.kulkarni@arm.com>
Change-Id: If9378064c41e0d14e6c789c71f8def594f89e220

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feat(sgi): firmware first error handling for Neoverse N2 CPU

RD-N2 platform variants have Neoverse N2 CPU that supports RAS
extensions. N2 CPU has error node that captures the faults occurring on
L1

feat(sgi): firmware first error handling for Neoverse N2 CPU

RD-N2 platform variants have Neoverse N2 CPU that supports RAS
extensions. N2 CPU has error node that captures the faults occurring on
L1, L2 tag and data RAMs. This node captures the error information in
its error records and generates fault handling interrupt on error event.

This patch adds reference implementation to demonstrate firmware-first
error handling of 1-bit CE that occur on CPU. On error event the error
handler reads the error records and ELx context information and forwards
it to secure partition. Secure partition creates a CPER record from this
error information. Finally the handler notifies the OS about the RAS
error using the SDEI notification mechanism.

Signed-off-by: Omkar Anand Kulkarni <omkar.kulkarni@arm.com>
Change-Id: I769550efee10b9a3d89056bca4bfeb2db4708998

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feat(arm): enable FHI PPI interrupt to report CPU errors

To handle the core corrected errors in the firmware, the FHI PPI
interrupt has to be enabled on all the cores. At boot, when the RAS
framewor

feat(arm): enable FHI PPI interrupt to report CPU errors

To handle the core corrected errors in the firmware, the FHI PPI
interrupt has to be enabled on all the cores. At boot, when the RAS
framework is initialized, only primary core is up and hence core FHI PPI
interrupt is enabled only on primary core. This patch adds support to
configure and enable core FHI interrupt for all the secondary cores as
part of their boot sequence.

Signed-off-by: Omkar Anand Kulkarni <omkar.kulkarni@arm.com>
Change-Id: I4b25152cb498fe975b9c770babb25aa9e01f9656

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chore(zynqmp): remove unused configuration from TSP

In ZynqMP, the function zynqmp_config_setup() is common between bl31
and bl32(TSP). This function initializes IPI configuration and
prints the chi

chore(zynqmp): remove unused configuration from TSP

In ZynqMP, the function zynqmp_config_setup() is common between bl31
and bl32(TSP). This function initializes IPI configuration and
prints the chip idcode and revision on the console, which is already
done in bl31 and redundant in bl32(TSP).

Remove the legacy code, reading the chip idcode and
revision information through direct register read.

Change-Id: I5da8e75a597ac9c4e1b56346e065d29e2be8787f
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>

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fix(zynqmp): resolve runtime error in TSP

TSP(bl32) requires secure interrupts to be handled at S-EL1.
Enable the ZynqMP to handle secure interrupts in S-EL1 by setting
GICV2_G0_FOR_EL3 to 0 in case

fix(zynqmp): resolve runtime error in TSP

TSP(bl32) requires secure interrupts to be handled at S-EL1.
Enable the ZynqMP to handle secure interrupts in S-EL1 by setting
GICV2_G0_FOR_EL3 to 0 in case of SPD=tspd build option.

For ZYNQMP_WDT_RESTART build option GICV2_G0_FOR_EL3 needs to be
enabled and thus for ZynqMP GICV2_G0_FOR_EL3 is set to 1 by default.
On GICv2, when GICV2_G0_FOR_EL3 is set to 1, Group 0 interrupts
target EL3. This allows GICv2 platforms to enable features requiring
EL3 interrupt type.

This also means that all GICv2 Group 0 interrupts are delivered
to EL3, and the Secure Payload interrupts needs to be synchronously
handed over to Secure EL1 for handling.

Change-Id: I7eb72c6588ab41730a74ece261050840646de037
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>

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chore(xilinx): reorder headers in assembly files

In tf-a-ci-scripts repo, change commit 8ffa3d571b(ci(static-checks):
correct include order for *.S macro headers) provides a fix related
to header fi

chore(xilinx): reorder headers in assembly files

In tf-a-ci-scripts repo, change commit 8ffa3d571b(ci(static-checks):
correct include order for *.S macro headers) provides a fix related
to header file include order in assembly files. With the above fix,
improper header order in assembly files has been detected.

Reorder the header includes in assembly files as per the update
in tf-a-ci-scripts.

Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Change-Id: I4a4f3c5bb73886dae234160b893470443f1424fc

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chore(xilinx): correct kernel doc warnings for missing functions

In commit b9d26cd3c4 ("chore(xilinx): replace fsbl with xbl"),
function and variable names were changed, but the corresponding
functi

chore(xilinx): correct kernel doc warnings for missing functions

In commit b9d26cd3c4 ("chore(xilinx): replace fsbl with xbl"),
function and variable names were changed, but the corresponding
function name in the functional documentation comments is not updated.
Update the function and variable names as per the above commit.

Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Change-Id: I7b777c21fe3673d29f809bf923eba38749f2c024

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Merge "feat(allwinner): use reset through scpi for warm/soft reset" into integration

Merge changes from topic "jc/errata_refactor" into integration

* changes:
refactor(cpus): convert Cortex-A72 to use cpu helpers
refactor(cpus): convert the Cortex-A72 to use the errata framework

Merge changes from topic "jc/errata_refactor" into integration

* changes:
refactor(cpus): convert Cortex-A72 to use cpu helpers
refactor(cpus): convert the Cortex-A72 to use the errata framework
refactor(cpus): reorder Cortex-A72 errata by ascending order

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Merge "refactor(cpus): use cpu errata wrappers for aarch64 hunter based cpus" into integration

feat(allwinner): use reset through scpi for warm/soft reset

On systems with SCP (running crust) scpi_system_reboot action
performs board-level (PMIC) reboot. This doesn't preserve RAM content
on A64

feat(allwinner): use reset through scpi for warm/soft reset

On systems with SCP (running crust) scpi_system_reboot action
performs board-level (PMIC) reboot. This doesn't preserve RAM content
on A64 PinePhone at least.

warm/soft system reset without RAM reset is required to get
pstore (persistent storage) in RAM working with Linux kernel. That is
very useful for oops/panic logging for post mortem analysis.

scpi_system_reset action performs reset via SoC reset (using watchdog)
and RAM content is preserved in this case. Linux kernel detects
system_reset2 support and uses it for warm reset automatically.

Change-Id: I1c21aa8f27c8e0395e2326034788693b59b80bc4
Signed-off-by: Andrey Skvortsov <andrej.skvortzov@gmail.com>

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Merge "feat(nuvoton): added support for npcm845x chip" into integration

docs(psa): doc AP/RSS interfaces for NV ctrs/ROTPK

Adding documentation for AP/RSS interfaces for NV counters and ROTPK

Change-Id: I38745bcc5d53317bab07bb81f11f9ba4551a224f
Signed-off-by: Lauren We

docs(psa): doc AP/RSS interfaces for NV ctrs/ROTPK

Adding documentation for AP/RSS interfaces for NV counters and ROTPK

Change-Id: I38745bcc5d53317bab07bb81f11f9ba4551a224f
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>

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