Merge "build(tools): avoid unnecessary link" into integration

build(tools): avoid unnecessary link

In their respective makefiles, cert_create, encrypt_fw and fiptool
depend on the --openssl phony target as a prerequisite. This forces
those tools to be re-linke

build(tools): avoid unnecessary link

In their respective makefiles, cert_create, encrypt_fw and fiptool
depend on the --openssl phony target as a prerequisite. This forces
those tools to be re-linked each time.

Move the dependencies on the --openssl target from the tools to their
makefiles all targets, to avoid unnecessary linking while preserving the
OpenSSL version printing done in the --openssl targets when in debug.

Fixes: cf2dd17ddda2 ("refactor(security): add OpenSSL 1.x compatibility")
Signed-off-by: Vincent Stehlé <vincent.stehle@arm.com>
Change-Id: I98a3ab30f36dffc253cecaaf3a57d2712522135d

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Merge "feat(morello): fdts: add CoreSight DeviceTree bindings" into integration

Merge "fix(n1sdp): configure platform specific secure SPIs" into integration

feat(qemu): add "neoverse-v1" cpu support

Add support to qemu "neoverse-v1" cpu for "qemu" ('virt') platform.

Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Change-Id: I4821115b5

feat(qemu): add "neoverse-v1" cpu support

Add support to qemu "neoverse-v1" cpu for "qemu" ('virt') platform.

Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Change-Id: I4821115b54ca596fe27cb9d74a95429cd3cb21d9

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Merge "feat(qemu): add "neoverse-v1" cpu support" into integration

feat(intel): platform enablement for Agilex5 SoC FPGA

This patch is used to enable platform enablement for
Agilex5 SoC FPGA.

New feature:
1. Added ATF->Zephyr boot option
2. Added xlat_v2 for MMU

feat(intel): platform enablement for Agilex5 SoC FPGA

This patch is used to enable platform enablement for
Agilex5 SoC FPGA.

New feature:
1. Added ATF->Zephyr boot option
2. Added xlat_v2 for MMU
3. Added ATF->Linux boot option
4. Added SMP support
5. Added HPS bridges support
6. Added EMULATOR support
7. Added DDR support
8. Added GICv3 Redistirbution init
9. Added SDMMC/NAND/Combo Phy support
10. Updated GIC as secure access
11. Added CCU driver support
12. Updated product name -> Agilex5
13. Updated register address based on y22ww52.2 RTL
14. Updated system counter freq to 400MHz

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: Ice82f3e4535527cfd01500d4d528402985f72009

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feat(intel): ccu driver for Agilex5 SoC FPGA

This patch is used to implement CCU driver for
Agilex5 SoC FPGA.

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: Ic5e38499c969486682761c

feat(intel): ccu driver for Agilex5 SoC FPGA

This patch is used to implement CCU driver for
Agilex5 SoC FPGA.

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: Ic5e38499c969486682761c00d9e050e60c883725

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feat(intel): vab support for Agilex5 SoC FPGA

This patch is used to implement VAB to support for
Agilex5 SoC FPGA.

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I421f11225cd549f35

feat(intel): vab support for Agilex5 SoC FPGA

This patch is used to implement VAB to support for
Agilex5 SoC FPGA.

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I421f11225cd549f35f06e87b8ad2c44b716b2a78

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feat(intel): sdmmc/nand/combo-phy/qspi driver for Agilex5 SoC FPGA

This patch is used to implement sdmmc/nand/combo-phy
driver to support Cadence IP for Agilex5 SoC FPGA.
1. Added SDMMC/NAND/COMBO-

feat(intel): sdmmc/nand/combo-phy/qspi driver for Agilex5 SoC FPGA

This patch is used to implement sdmmc/nand/combo-phy
driver to support Cadence IP for Agilex5 SoC FPGA.
1. Added SDMMC/NAND/COMBO-PHY support.
2. Updated product name -> Agilex5
3. Updated QSPI base address

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I6db689d2b784c9f59a25701ab34517f6f6b0a0e6

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feat(intel): ddr driver for Agilex5 SoC FPGA

This patch is used to implement ddr driver to
support IO96b for Agilex5 SoC FPGA.
1. Added DDR support.
2. Updated product name -> Agilex5

Signed-off-

feat(intel): ddr driver for Agilex5 SoC FPGA

This patch is used to implement ddr driver to
support IO96b for Agilex5 SoC FPGA.
1. Added DDR support.
2. Updated product name -> Agilex5

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: Ibda053de6dbec4a0f12f011d8feeb6c5890fc7a4

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feat(intel): power manager for Agilex5 SoC FPGA

This patch is used to implement power manager data
support for Agilex5 SoC FPGA.
1. Added power manager support.
2. Updated product name -> Agilex5

feat(intel): power manager for Agilex5 SoC FPGA

This patch is used to implement power manager data
support for Agilex5 SoC FPGA.
1. Added power manager support.
2. Updated product name -> Agilex5

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: If0630c5088a1bc63dff64b1aab225fc70effa6e3

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feat(intel): cold/warm reset and smp support for Agilex5 SoC FPGA

This patch is used to implement
1. Cold/Warm reset and SMP support for
Agilex5 SoC FPGA
2. Updated product name -> Agilex5

Signe

feat(intel): cold/warm reset and smp support for Agilex5 SoC FPGA

This patch is used to implement
1. Cold/Warm reset and SMP support for
Agilex5 SoC FPGA
2. Updated product name -> Agilex5

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I2c0645bcbf3a5907a4c79f35cffe674920b48f9d

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feat(intel): reset manager support for Agilex5 SoC FPGA

This patch is used to enable reset manager support
for Agilex5 SoC FPGA.
1. Added HPS bridges support
a. SOC2FPGA
b. LWSOC2FPGA
c. F2SD

feat(intel): reset manager support for Agilex5 SoC FPGA

This patch is used to enable reset manager support
for Agilex5 SoC FPGA.
1. Added HPS bridges support
a. SOC2FPGA
b. LWSOC2FPGA
c. F2SDRAM
d. F2SOC
2. Added EMULATOR support
3. Added WDT support
4. Updated product name -> Agilex5
5. Added SMP support

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: Icab15b25f787fdccce1de75d102604db23beaf11

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feat(intel): mailbox and SMC support for Agilex5 SoC FPGA

This patch is used to enable mailbox and SMC support
for Agilex5 SoC FPGA.
1. Enabled mailbox and SMC support.
2. Updated product name ->

feat(intel): mailbox and SMC support for Agilex5 SoC FPGA

This patch is used to enable mailbox and SMC support
for Agilex5 SoC FPGA.
1. Enabled mailbox and SMC support.
2. Updated product name -> Agilex5
3. Updated register address based on y22ww52.2 RTL
4. Updated TSN register base address

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I152bee5668b96ef599ded09945167f27a71f23fe

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feat(intel): system manager support for Agilex5 SoC FPGA

This patch is used to implement system manager data
support for Agilex5 SoC FPGA.

1. Initial SM bring up
2. Support Candence SDMMC/NAND/CO

feat(intel): system manager support for Agilex5 SoC FPGA

This patch is used to implement system manager data
support for Agilex5 SoC FPGA.

1. Initial SM bring up
2. Support Candence SDMMC/NAND/COMBO PHY
3. Updated product name -> Agilex5
4. Updated register address based on y22ww52.2 RTL

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I12712bddfb67e36a2bf56d2d98ea4ca3037f0a82

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feat(intel): memory controller support for Agilex5 SoC FPGA

This patch is used to enable memory controller support
for Agilex5 SoC FPGA.
1. Added memory controller support.
2. Updated product name

feat(intel): memory controller support for Agilex5 SoC FPGA

This patch is used to enable memory controller support
for Agilex5 SoC FPGA.
1. Added memory controller support.
2. Updated product name -> Agilex5

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I8381b82eeed939b970a7410a6181a514f2c90caa

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feat(intel): clock manager support for Agilex5 SoC FPGA

This patch is used to enable clock manager support
for Agilex5 SoC FPGA.
1. Added clock manager support.
2. Updated product name -> Agilex5

feat(intel): clock manager support for Agilex5 SoC FPGA

This patch is used to enable clock manager support
for Agilex5 SoC FPGA.
1. Added clock manager support.
2. Updated product name -> Agilex5
3. Updated register address based on y22ww52.2 RTL
4. Standardized handoff handler.

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: Ic4c57a1955136ef7d22253c3ca52226e5620751b

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feat(intel): mmc support for Agilex5 SoC FPGA

This patch is used to enable MMC support for
Agilex5 SoC FPGA.
1. Added MMC support.
2. Updated product name -> Agilex5
3. Updated register address b

feat(intel): mmc support for Agilex5 SoC FPGA

This patch is used to enable MMC support for
Agilex5 SoC FPGA.
1. Added MMC support.
2. Updated product name -> Agilex5
3. Updated register address based on y22ww52.2 RTL

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I47f5c7f063fc443f29c2af612121abe672ed422b

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feat(intel): uart support for Agilex5 SoC FPGA

This patch is used to enable UART & WDT support
for Agilex5 SoC FPGA.

1. Added watchdog support.
2. Updated product name -> Agilex5

Signed-off-by:

feat(intel): uart support for Agilex5 SoC FPGA

This patch is used to enable UART & WDT support
for Agilex5 SoC FPGA.

1. Added watchdog support.
2. Updated product name -> Agilex5

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I9346cfde6e033026e4c1e612250e9521bc6b0d47

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feat(intel): pinmux, peripheral and Handoff support for Agilex5 SoC FPGA

This patch is used to enable pinmux, peripheral and handoff support
for Agilex5 SoC FPGA.
1. Initial handoff bring up
2. Ad

feat(intel): pinmux, peripheral and Handoff support for Agilex5 SoC FPGA

This patch is used to enable pinmux, peripheral and handoff support
for Agilex5 SoC FPGA.
1. Initial handoff bring up
2. Added power manager handoff implementation
3. Added sdram handoff implementation
4. Updated product name -> Agilex5
5. Updated register address based on y22ww52.2 RTL

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I4b0176bc86c57823127bf41086306015d702577d

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Merge "chore(xilinx): reorder include files as per TF-A guidelines" into integration

Merge "fix(versal-net): correct device node indexes" into integration

Merge "fix(st-uart): correctly check UART enabled in flush fonction" into integration

refactor(amu): separate the EL2 and EL3 enablement code

Combining the EL2 and EL3 enablement code necessitates that it must be
called at el3_exit, which is the only place with enough context to make

refactor(amu): separate the EL2 and EL3 enablement code

Combining the EL2 and EL3 enablement code necessitates that it must be
called at el3_exit, which is the only place with enough context to make
the decision of what needs to be set.
Decouple them to allow them to be called from elsewhere. Also take
some time to clarify and simplify AMU code.

The sanity check in the context_restore() is now wrong, as the cpu may
turn off on suspend, thus resetting the value of the counter enables.
Remove it.

Finally, this completes the migration to cm_manage_extensions_el3() and
manage_extensions_nonsecure() so manage_extensions_nonsecure_mixed() is
being removed.

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: I66399132364c32be66017506bb54cbadd8485577

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