fix(el3-spmc): fix incorrect CASSERT

Check that the size of desc->emad_count is 4, not that sizeof(int) is
nonzero. Also improve a comment.

Change-Id: I8bf69b637158ddffe2d08aed3d9879a4d7fd3514
Sig

fix(el3-spmc): fix incorrect CASSERT

Check that the size of desc->emad_count is 4, not that sizeof(int) is
nonzero. Also improve a comment.

Change-Id: I8bf69b637158ddffe2d08aed3d9879a4d7fd3514
Signed-off-by: Demi Marie Obenour <demiobenour@gmail.com>

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Merge changes from topic "bk/context_refactor" into integration

* changes:
refactor(psci): extract cm_prepare_el3_exit_ns() to a common location
refactor(cm): set MDCR_EL3/CPTR_EL3 bits in respe

Merge changes from topic "bk/context_refactor" into integration

* changes:
refactor(psci): extract cm_prepare_el3_exit_ns() to a common location
refactor(cm): set MDCR_EL3/CPTR_EL3 bits in respective feat_init_el3() only
fix(cm): set MDCR_EL3.{NSPBE, STE} explicitly
refactor(cm): factor out EL2 register setting when EL2 is unused

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refactor(psci): extract cm_prepare_el3_exit_ns() to a common location

PSCI on and suspend wakeup both end with a cm_prepare_el3_exit_ns() call.
Since they are equivalent to the caller, move the call

refactor(psci): extract cm_prepare_el3_exit_ns() to a common location

PSCI on and suspend wakeup both end with a cm_prepare_el3_exit_ns() call.
Since they are equivalent to the caller, move the call to just after the
*_finish calls to deduplicate it.

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: I05c16dc6613aba357d20cc39cc43aab803d675e0

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refactor(cm): set MDCR_EL3/CPTR_EL3 bits in respective feat_init_el3() only

These bits (MDCR_EL3.{NSTB, NSTBE, TTRF, TPM}, CPTR_EL3.TTA) only affect
EL2 (and lower) execution. Each feat_init_el3() i

refactor(cm): set MDCR_EL3/CPTR_EL3 bits in respective feat_init_el3() only

These bits (MDCR_EL3.{NSTB, NSTBE, TTRF, TPM}, CPTR_EL3.TTA) only affect
EL2 (and lower) execution. Each feat_init_el3() is called long before
any lower EL has had a chance to execute, so setting the bits at reset
is redundant. Removing them from reset code also improves readability of
the immutable EL3 state.

Preserve the original intention for the TTA bit of "enabled for NS and
disabled everywhere else" (inferred from commit messages d4582d3088 and
2031d6166a and the comment). This is because CPTR_EL3 will be contexted
and so everyone will eventually get whatever NS has anyway.

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: I3d24b45d3ea80882c8e450b2d9db9d5531facec1

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fix(cm): set MDCR_EL3.{NSPBE, STE} explicitly

With the introduction of FEAT_RME MDCR_EL3 bits NSPB and NSPBE depend on
each other. The enable code relies on the register being initialised to
zero an

fix(cm): set MDCR_EL3.{NSPBE, STE} explicitly

With the introduction of FEAT_RME MDCR_EL3 bits NSPB and NSPBE depend on
each other. The enable code relies on the register being initialised to
zero and omits to reset NSPBE. However, this is not obvious. Reset the
bit explicitly to document this.

Similarly, reset the STE bit , since it's part of the feature enablement.

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: I3714507bae10042cdccd2b7bc713b31d4cdeb02f

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refactor(cm): factor out EL2 register setting when EL2 is unused

A bunch of registers need to be initialized when EL2 is unused. There
are a lot of them which makes cm_prepare_el3_exit() quite unrea

refactor(cm): factor out EL2 register setting when EL2 is unused

A bunch of registers need to be initialized when EL2 is unused. There
are a lot of them which makes cm_prepare_el3_exit() quite unreadable.
Put them in their own function to improve this.

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: If07954ed799643f89f177411d4266bb7c21cd394

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fix(cpus): workaround for Neoverse V2 erratum 2801372

Neoverse V2 erratum 2801372 is a Cat B erratum that applies to
all revisions <=r0p1 and is fixed in r0p2. The workaround is to
insert a dsb befo

fix(cpus): workaround for Neoverse V2 erratum 2801372

Neoverse V2 erratum 2801372 is a Cat B erratum that applies to
all revisions <=r0p1 and is fixed in r0p2. The workaround is to
insert a dsb before the isb in the power down sequence.

This errata is explained in SDEN 2332927 available at:
https://developer.arm.com/documentation/SDEN2332927

Change-Id: I8716b9785a67270a72ae329dc49a2f2239dfabff
Signed-off-by: Moritz Fischer <moritzf@google.com>

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Merge "refactor(el3-runtime): move interrupt exception handler from macro to a function" into integration

refactor(el3-runtime): move interrupt exception handler from macro to a function

interrupt exception handler in vector entry is used as a asm macro
(added as inline code) instead of a function call.

refactor(el3-runtime): move interrupt exception handler from macro to a function

interrupt exception handler in vector entry is used as a asm macro
(added as inline code) instead of a function call. Since we have limited
space (0x80) for a vector entry there is a chance that it may overflow
in the future.

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: Ieb59f249c58b52e56e0217268fa4dc40b420f8d3

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Merge "fix(fvp): adjust BL2 maximum size as per total SRAM size" into integration

refactor(cpus): add Cortex-A17 errata framework information

Change-Id: I19d096edf47c1a9f47e79e9bb95984ce2102fad4
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

fix(fvp): resolve broken workaround reference

The workaround for CVE 2015-5715 was renamed many years ago, however,
Cortex-A17 and A9 didn't see this change.

Change-Id: I553c8b09543263bca2a34eaef67

fix(fvp): resolve broken workaround reference

The workaround for CVE 2015-5715 was renamed many years ago, however,
Cortex-A17 and A9 didn't see this change.

Change-Id: I553c8b09543263bca2a34eaef670af0424999cfe
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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fix(fvp): adjust BL2 maximum size as per total SRAM size

Adjusted BL2 maximum size as per total SRAM size.

Change-Id: Ic3b398574a17e8a784e7c4dbe3fe69d1fb2b5e16
Signed-off-by: Manish V Badarkhe <Man

fix(fvp): adjust BL2 maximum size as per total SRAM size

Adjusted BL2 maximum size as per total SRAM size.

Change-Id: Ic3b398574a17e8a784e7c4dbe3fe69d1fb2b5e16
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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Merge "docs(maintainers): update AMD maintainers list" into integration

Merge "feat(mte): adds feature detection for MTE_PERM" into integration

docs(maintainers): update AMD maintainers list

Maintainers for AMD platform ports has been updated.
"Amit Nagal" and "Akshay Belsare" are added to the list.

Change-Id: Ia64e1ec6c2f80515054730d307d4

docs(maintainers): update AMD maintainers list

Maintainers for AMD platform ports has been updated.
"Amit Nagal" and "Akshay Belsare" are added to the list.

Change-Id: Ia64e1ec6c2f80515054730d307d41b0060d3dcc7
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>

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feat(mte): adds feature detection for MTE_PERM

Adds feature detection for v8.9 feature FEAT_MTE_PERM. Adds respective
ID_AA64PFR2_EL1 definitions and ENABLE_FEAT_MTE_PERM define.

Change-Id: If24b42

feat(mte): adds feature detection for MTE_PERM

Adds feature detection for v8.9 feature FEAT_MTE_PERM. Adds respective
ID_AA64PFR2_EL1 definitions and ENABLE_FEAT_MTE_PERM define.

Change-Id: If24b42f1207154e639016b0b840b2d91c6ee13d4
Signed-off-by: Maksims Svecovs <maksims.svecovs@arm.com>
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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chore(docs): update march utility details

commit@7794d6c8f8c44acc14fbdc5ada5965310056be1e added a march utility
but the details were not updated in docs.

Update docs to provide a glimpse of march u

chore(docs): update march utility details

commit@7794d6c8f8c44acc14fbdc5ada5965310056be1e added a march utility
but the details were not updated in docs.

Update docs to provide a glimpse of march utility added.

Change-Id: I696cb9a701a30d7bf36a1ecd38a80d07df1fd551
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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Merge changes from topic "msm8916-plats" into integration

* changes:
docs(msm8916): document new platforms
feat(msm8916): add port for MDM9607
refactor(msm8916): handle single core platforms

Merge changes from topic "msm8916-plats" into integration

* changes:
docs(msm8916): document new platforms
feat(msm8916): add port for MDM9607
refactor(msm8916): handle single core platforms
feat(msm8916): add port for MSM8939
feat(msm8916): power on L2 caches for secondary clusters
feat(msm8916): initialize CCI-400 for multiple clusters
refactor(msm8916): handle multiple CPU clusters
feat(msm8916): add port for MSM8909
feat(msm8916): clear CACHE_LOCK for MMU-500 r2p0+
style(msm8916): add missing braces to while statements

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docs(msm8916): document new platforms

Document the new platform build options for the MSM8916 port which now
supports multiple similar Qualcomm SoCs:

- Snapdragon 410 (PLAT=msm8916) as before
-

docs(msm8916): document new platforms

Document the new platform build options for the MSM8916 port which now
supports multiple similar Qualcomm SoCs:

- Snapdragon 410 (PLAT=msm8916) as before
- Snapdragon 615 (PLAT=msm8939)
- Snapdragon 210 (PLAT=msm8909)
- Snapdragon X5 Modem (PLAT=mdm9607)

The latter two use AArch32-only ARM Cortex-A7 cores that only support
using BL32/SP_MIN and not BL31 on AArch64.

Change-Id: I9fffe60dd0ad2acc18f006f11e91854b9e8dcb8f
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>

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feat(msm8916): add port for MDM9607

The Qualcomm X5 Modem (MDM9607) SoC is very similar to the existing
MSM8916, except for:

- Single core ARM Cortex-A7
- No GPU
- MMU-500 r2p4 instead of r0p

feat(msm8916): add port for MDM9607

The Qualcomm X5 Modem (MDM9607) SoC is very similar to the existing
MSM8916, except for:

- Single core ARM Cortex-A7
- No GPU
- MMU-500 r2p4 instead of r0p0 (need to clear CACHE_LOCK bit)
- Different default BL31/BL33 address and UART number

Make the existing MSM8916 platform port usable for MDM9607 as well by
adding some minimal if statements where necessary plus the platform
make files for mdm9607.

Change-Id: I4dd02c8e29af6282d8d828c3027c5e333459ba36
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>

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refactor(msm8916): handle single core platforms

Some Qualcomm modem platforms (MDM*) are quite similar to MSM8916
except that there is just a single CPU core. This requires some special
handling:

refactor(msm8916): handle single core platforms

Some Qualcomm modem platforms (MDM*) are quite similar to MSM8916
except that there is just a single CPU core. This requires some special
handling:

- There is no GPU so the GPU SMMU also does not exist.
- Looking closely at dumps of the MMIO register regions reveals that
some of the register addresses are slightly different.

Add the necessary checks for this to allow building for those
platforms.

No functional change for existing platforms.

Change-Id: I0380ac3734876243e970a55d8bec5a8247175343
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>

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feat(msm8916): add port for MSM8939

The Qualcomm Snapdragon 615 (MSM8939) SoC is very similar to the
existing MSM8916, except for:

- Two clusters with ARM Cortex-A53 cores
- CCI-400

Make the e

feat(msm8916): add port for MSM8939

The Qualcomm Snapdragon 615 (MSM8939) SoC is very similar to the
existing MSM8916, except for:

- Two clusters with ARM Cortex-A53 cores
- CCI-400

Make the existing MSM8916 platform port usable for MSM8939 as well by
adding some minimal if statements where necessary plus the platform
make files for msm8939.

Change-Id: I8cda83dc642f62222f984a42eec14de5df4c11e3
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>

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feat(msm8916): power on L2 caches for secondary clusters

On platforms with multiple CPU clusters the L2 cache will be only on
for the cluster of the boot CPU. Add the necessary sequence to power it

feat(msm8916): power on L2 caches for secondary clusters

On platforms with multiple CPU clusters the L2 cache will be only on
for the cluster of the boot CPU. Add the necessary sequence to power it
up for secondary clusters similar to the CPU boot sequence.

No functional change for platforms with a single cluster. The new code
is discarded entirely in this case.

Change-Id: I3d3bce519a8a10ef5278d74d81acf59123e00454
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>

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feat(msm8916): initialize CCI-400 for multiple clusters

The MSM8939 SoC is very similar to MSM8916 but uses an ARM CCI-400
for cache coherence between the two CPU clusters. Add the necessary
code to

feat(msm8916): initialize CCI-400 for multiple clusters

The MSM8939 SoC is very similar to MSM8916 but uses an ARM CCI-400
for cache coherence between the two CPU clusters. Add the necessary
code to initialize it with the existing driver.

No functional change for platforms with a single cluster. The CCI
related code is discarded entirely in this case.

Change-Id: I041d60222d8d2aeca53b392934c87280c66b0db0
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>

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